hobold (hobold.delete@this.vectorizer.org) on June 27, 2022 12:09 pm wrote:
> Anon (no.delete@this.thanks.com) on June 27, 2022 3:34 am wrote:
> > Groo (charlie.delete@this.semiaccurate.com) on June 26, 2022 9:39 am wrote:
> > > It is a tad more expensive but not a significant cost in relation to a finished wafer on a modern
> > > process. The biggest reason you don't want to do it is the loss of edge area for I/O.
> >
> > I guess the obvious answer to that would be triangular dies? They still tesselate
> > nicely, but they give you higher edge area for a given die size.
>
> I was under the impression that the structures etched into
> the wafer are aligned with the silicon crystal lattice?
>
> I believe silicon crystallizes as a face centered cubic lattice. That would be compatible
> with some cartesian 2D grid on the wafer surface (i.e. the usual right angles and
> rectangles), but not fully compatible with a honeycomb/hexagonal grid[*].

Original dies were built on 2 - 3 MICRON design rules. I don't think the crystal structure mattered much at those sized :-)

Also, Silicon is much like Carbon, so not exactly square ...