By: Adrian (a.delete@this.acm.org), June 27, 2022 10:01 pm
Room: Moderated Discussions
Mark Roulo (nothanks.delete@this.xxx.com) on June 27, 2022 6:02 pm wrote:
> hobold (hobold.delete@this.vectorizer.org) on June 27, 2022 12:09 pm wrote:
> > Anon (no.delete@this.thanks.com) on June 27, 2022 3:34 am wrote:
> > > Groo (charlie.delete@this.semiaccurate.com) on June 26, 2022 9:39 am wrote:
> > > > It is a tad more expensive but not a significant cost in relation to a finished wafer on a modern
> > > > process. The biggest reason you don't want to do it is the loss of edge area for I/O.
> > >
> > > I guess the obvious answer to that would be triangular dies? They still tesselate
> > > nicely, but they give you higher edge area for a given die size.
> >
> > I was under the impression that the structures etched into
> > the wafer are aligned with the silicon crystal lattice?
> >
> > I believe silicon crystallizes as a face centered cubic lattice. That would be compatible
> > with some cartesian 2D grid on the wafer surface (i.e. the usual right angles and
> > rectangles), but not fully compatible with a honeycomb/hexagonal grid[*].
>
> Original dies were built on 2 - 3 MICRON design rules. I don't
> think the crystal structure mattered much at those sized :-)
>
> Also, Silicon is much like Carbon, so not exactly square ...
Almost all silicon wafers are sliced to have their plane surface parallel with 1 of 2 crystallographic directions, either with the direction "100", where squares on the surface have the edges parallel with crystallographic directions, or with the direction "111", where regular triangles or hexagons on the surface have the edges parallel with crystallographic directions.
The direction "100" (squares) is preferred for MOS transistors, i.e. for most modern CMOS processes, while the direction "111" (traingles/hexagons) was preferred for bipolar transistors, so it was used in most old IC manufacturing processes.
For slicing the wafer into dies, which is started either with diamond cutters or with lasers, the alignment of the edges to the crystallographic directions does not matter much (though splitting the wafer after scratching requires smaller forces along certain directions).
On the other hand, some of the chemical etching methods used during the manufacturing process have very different etching rates depending on the direction, so the transistors and any other devices must be precisely aligned with known crystallographic directions (which are marked on the wafer by cutting on a side either a small flat segment or a notch).
> hobold (hobold.delete@this.vectorizer.org) on June 27, 2022 12:09 pm wrote:
> > Anon (no.delete@this.thanks.com) on June 27, 2022 3:34 am wrote:
> > > Groo (charlie.delete@this.semiaccurate.com) on June 26, 2022 9:39 am wrote:
> > > > It is a tad more expensive but not a significant cost in relation to a finished wafer on a modern
> > > > process. The biggest reason you don't want to do it is the loss of edge area for I/O.
> > >
> > > I guess the obvious answer to that would be triangular dies? They still tesselate
> > > nicely, but they give you higher edge area for a given die size.
> >
> > I was under the impression that the structures etched into
> > the wafer are aligned with the silicon crystal lattice?
> >
> > I believe silicon crystallizes as a face centered cubic lattice. That would be compatible
> > with some cartesian 2D grid on the wafer surface (i.e. the usual right angles and
> > rectangles), but not fully compatible with a honeycomb/hexagonal grid[*].
>
> Original dies were built on 2 - 3 MICRON design rules. I don't
> think the crystal structure mattered much at those sized :-)
>
> Also, Silicon is much like Carbon, so not exactly square ...
Almost all silicon wafers are sliced to have their plane surface parallel with 1 of 2 crystallographic directions, either with the direction "100", where squares on the surface have the edges parallel with crystallographic directions, or with the direction "111", where regular triangles or hexagons on the surface have the edges parallel with crystallographic directions.
The direction "100" (squares) is preferred for MOS transistors, i.e. for most modern CMOS processes, while the direction "111" (traingles/hexagons) was preferred for bipolar transistors, so it was used in most old IC manufacturing processes.
For slicing the wafer into dies, which is started either with diamond cutters or with lasers, the alignment of the edges to the crystallographic directions does not matter much (though splitting the wafer after scratching requires smaller forces along certain directions).
On the other hand, some of the chemical etching methods used during the manufacturing process have very different etching rates depending on the direction, so the transistors and any other devices must be precisely aligned with known crystallographic directions (which are marked on the wafer by cutting on a side either a small flat segment or a notch).
