Brett (ggtgp.delete@this.yahoo.com) on July 2, 2022 2:35 pm wrote:
> Math Nerd (math.nerd.delete@this.nerds.com) on July 1, 2022 9:20 pm wrote:
> > > triangles are better than rectangular or hexagonal dies at minimizing wasted area, and much easier to prove.
> >
> > Can someone please explain why triangular die are better than
> > hexagonal die at minimizing wasted area on circular wafers?
> >
> > To be a fair comparison, the die of different shapes would have to have the same area because smaller
> > die would certainly waste less area than larger die, regardless of shape. A hexagon with the same
> > area as an equilateral triangle has about .8 the height and .8 the width of the equilateral triangle.
> > A hexagon with the same area as an isosceles right triangle has about .8 the height and .9 the
> > width of the isosceles right triangle. This smaller height and width allows the hexagon to get
> > closer to the edge of a circle without going outside, which reduces wasted area.
> >
> > An advantage of isosceles right triangular die is that when near the edge of the circle, if
> > two of them (forming a square) had one corner of the square outside the circle, a single triangle
> > could be used there. A disadvantage of isosceles right triangular die, as mentioned earlier,
> > is that they have a bigger width and height than hexagonal die of the same area.
> >
> > For triangular die, the wafer would need to be rotated in the lithography machine (stepper) or there would
> > need to be multiple different versions of the same design
> > on the mask. For equilateral triangles, about half
> > the triangles would be printed with the vertex pointing
> > up and the other half would be printed with the vertex
> > pointing down. For right triangular die, 4 different directions of the hypotenuse would need to be printed
> > to minimize wasted area. The hypotenuse direction needed
> > on the left edge of the wafer is different from the
> > hypotenuse direction needed on the right edge of the wafer
> > and same for top vs bottom. A more practical problem
> > with triangular die, pointed out by Adrian, is the difficulty of routing wires in the corners.
> >
> > The reason I suspect hexagonal die waste less area than rectangular die is that when rectangular die are
> > trying to match an angle other than horizontal or vertical, there are big stair steps of wasted area. With
> > hexagonal and equilateral triangular die, there are 4 angled directions (corresponding to perpendicular
> > axes rotated 60 degrees) where the wasted area of stair steps is smaller than for rectangular die.
>
> As most CPU’s have two or more memory busses if you spread all your connections
> on both half’s of the die you can salvage most of the dies on the edge.
>
> Since you have to put a pattern on the full wafer so polishing works evenly you have some CPU dies that are
> more than half off the wafer, and many of those will work in a reduced mode if you are smart in your layout.
> If only two cores of 8 work, fine, sell it in the low end laptop market, it was a one third sized die anyway.

I think this would require non-trivial changes to the way the dies are laid out.



Notice the IGPU on one end, the memory controller on the other and the ring bus in the middle?

I'm not claiming that this couldn't be done, but it won't be done trivially. The most straightforward way to do this is to go to chiplets, but even the AMD chiplets come with eight cores in a core complex.

The chips on the edge of the wafer are the ones that have lower yield, too, so that adds another negative because you won't save as many partials as you might expect just looking at average yield per wafer.