Die shape that minimizes wasted area on circular wafers

By: Doug S (foo.delete@this.bar.bar), July 2, 2022 6:44 pm
Room: Moderated Discussions
Mark Roulo (nothanks.delete@this.xxx.com) on July 2, 2022 4:41 pm wrote:
> Brett (ggtgp.delete@this.yahoo.com) on July 2, 2022 2:35 pm wrote:
> > Math Nerd (math.nerd.delete@this.nerds.com) on July 1, 2022 9:20 pm wrote:
> > > > triangles are better than rectangular or hexagonal dies at minimizing wasted area, and much easier to prove.
> > >
> > > Can someone please explain why triangular die are better than
> > > hexagonal die at minimizing wasted area on circular wafers?
> > >
> > > To be a fair comparison, the die of different shapes would have to have the same area because smaller
> > > die would certainly waste less area than larger die, regardless of shape. A hexagon with the same
> > > area as an equilateral triangle has about .8 the height and .8 the width of the equilateral triangle.
> > > A hexagon with the same area as an isosceles right triangle has about .8 the height and .9 the
> > > width of the isosceles right triangle. This smaller height and width allows the hexagon to get
> > > closer to the edge of a circle without going outside, which reduces wasted area.
> > >
> > > An advantage of isosceles right triangular die is that when near the edge of the circle, if
> > > two of them (forming a square) had one corner of the square outside the circle, a single triangle
> > > could be used there. A disadvantage of isosceles right triangular die, as mentioned earlier,
> > > is that they have a bigger width and height than hexagonal die of the same area.
> > >
> > > For triangular die, the wafer would need to be rotated in the lithography machine (stepper) or there would
> > > need to be multiple different versions of the same design
> > > on the mask. For equilateral triangles, about half
> > > the triangles would be printed with the vertex pointing
> > > up and the other half would be printed with the vertex
> > > pointing down. For right triangular die, 4 different directions of the hypotenuse would need to be printed
> > > to minimize wasted area. The hypotenuse direction needed
> > > on the left edge of the wafer is different from the
> > > hypotenuse direction needed on the right edge of the wafer
> > > and same for top vs bottom. A more practical problem
> > > with triangular die, pointed out by Adrian, is the difficulty of routing wires in the corners.
> > >
> > > The reason I suspect hexagonal die waste less area than rectangular die is that when rectangular die are
> > > trying to match an angle other than horizontal or vertical, there are big stair steps of wasted area. With
> > > hexagonal and equilateral triangular die, there are 4 angled directions (corresponding to perpendicular
> > > axes rotated 60 degrees) where the wasted area of stair steps is smaller than for rectangular die.
> >
> > As most CPU’s have two or more memory busses if you spread all your connections
> > on both half’s of the die you can salvage most of the dies on the edge.
> >
> > Since you have to put a pattern on the full wafer so polishing works evenly you have some CPU dies that are
> > more than half off the wafer, and many of those will work
> > in a reduced mode if you are smart in your layout.
> > If only two cores of 8 work, fine, sell it in the low end
> > laptop market, it was a one third sized die anyway.
>
> I think this would require non-trivial changes to the way the dies are laid out.
>
> Alder Lake
>
> Notice the IGPU on one end, the memory controller on the other and the ring bus in the middle?


Not only that, but while it may make sense to spread the memory controllers around the edges (Apple did that on M1 Pro/Max specifically to allow a "chop" die) not everything works like that. You can't spread the GPU cores all over the die without hurting performance because of the increased power and latency to communicate between the disparate pieces of your once unified GPU. There's a reason we generally see all the cores (of whatever type) in a self contained block - they share resources like cache which would be impacted if they were broken into smaller units spread across the die.

Then you have things that are currently only one of, like various I/Os or units like an HEVC encoder. What is Qualcomm going to do on its SoCs that include a cellular modem? Pretty sure you can't break that up into pieces with reduced functionality, that's going to be all or nothing.
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TopicPosted ByDate
OK dumb question timeDoug S2022/06/24 01:31 PM
  OK dumb question timeanon52022/06/24 01:38 PM
  Silicon ingots are round.Mark Roulo2022/06/24 02:29 PM
    Silicon ingots are round.Squarehead2022/06/24 02:38 PM
      Silicon ingots are round.Mark2022/06/24 03:00 PM
        Silicon ingots are round.Gary Kopp2022/06/24 03:20 PM
      Silicon ingots are round.Adrian2022/06/24 11:34 PM
    Silicon ingots are round.tarlinian2022/06/24 03:38 PM
      Silicon ingots are round.Doug S2022/06/24 11:13 PM
        Silicon ingots are round.anon2022/06/25 11:34 AM
          Silicon ingots are round.Doug S2022/06/25 11:39 AM
            Silicon ingots are round.Groo2022/06/26 09:41 AM
              Silicon ingots are round.Doug S2022/06/26 12:05 PM
                Silicon ingots are round.Gtoo2022/06/26 02:55 PM
          Silicon ingots are round.rwessel2022/06/25 11:43 AM
            Not reallyGroo2022/06/26 09:39 AM
              Not reallydmcq2022/06/26 10:56 AM
                Not reallyGroo2022/06/26 02:58 PM
              Not reallyanon22022/06/26 05:22 PM
              Why not triangles? Anon2022/06/27 03:34 AM
                Why not triangles? Math Nerd2022/06/27 04:52 AM
                Why not triangles? Math Nerd2022/06/27 05:45 AM
                  Don't forget Penrose Tiling (NT)ananon2022/06/27 06:06 AM
                  Why not triangles? Doug S2022/06/27 07:43 AM
                  Why not triangles? Anon2022/06/27 08:33 AM
                    Die shape that minimizes wasted area on circular wafersMath Nerd2022/07/01 09:20 PM
                      Die shape that minimizes wasted area on circular wafersBrett2022/07/02 02:35 PM
                        Die shape that minimizes wasted area on circular wafersMath Nerd2022/07/02 04:15 PM
                        Die shape that minimizes wasted area on circular wafersMark Roulo2022/07/02 04:41 PM
                          Die shape that minimizes wasted area on circular wafersDoug S2022/07/02 06:44 PM
                          Die shape that minimizes wasted area on circular wafersBrett2022/07/03 12:31 AM
                            Die shape that minimizes wasted area on circular wafersAdrian2022/07/03 10:25 PM
                              Die shape that minimizes wasted area on circular wafersanon22022/07/03 11:33 PM
                                Die shape that minimizes wasted area on circular wafersBrett2022/07/04 12:45 AM
                                  Die shape that minimizes wasted area on circular wafersdmcq2022/07/04 06:09 AM
                                    Die shape that minimizes wasted area on circular wafersJames2022/07/04 09:52 AM
                                      Die shape that minimizes wasted area on circular wafersdmcq2022/07/04 10:26 AM
                                        Die shape that minimizes wasted area on circular wafersAdrian2022/07/05 03:28 AM
                                      Cannon Lake vs Kaby LakeMark Roulo2022/07/04 10:30 AM
                                        C-class bonusesblue2022/07/04 12:27 PM
                                          C-class bonusesanonymou52022/07/04 03:23 PM
                                  Die shape that minimizes wasted area on circular wafersanon22022/07/04 06:53 AM
                                    Die shape that minimizes wasted area on circular wafersBrett2022/07/04 12:32 PM
                                      Die shape that minimizes wasted area on circular wafersFoyle2022/07/04 01:30 PM
                                        Die shape that minimizes wasted area on circular wafersAnon2022/07/04 01:37 PM
                                          What is a mirrored die?Mark Roulo2022/07/04 02:59 PM
                                            What is a mirrored die?Brett2022/07/04 03:32 PM
                                              What is a mirrored die?Doug S2022/07/04 10:08 PM
                                        Die shape that minimizes wasted area on circular wafersanonymou52022/07/04 03:12 PM
                                          Die shape that minimizes wasted area on circular wafersFoyle2022/07/05 10:41 AM
                                      Die shape that minimizes wasted area on circular wafersanon22022/07/04 04:52 PM
                                        Die shape that minimizes wasted area on circular wafersUngo2022/07/05 06:24 PM
                                          Die shape that minimizes wasted area on circular wafersBrett2022/07/05 07:56 PM
                                            Die shape that minimizes wasted area on circular wafersanonymou52022/07/06 05:46 AM
                                              Die shape that minimizes wasted area on circular wafersdmcq2022/07/06 02:55 PM
                                                Die shape that minimizes wasted area on circular wafersMark Roulo2022/07/06 04:09 PM
                                                Die shape that minimizes wasted area on circular wafersDoug S2022/07/06 05:31 PM
                                      Example of mirrored wafer?Mark Roulo2022/07/04 06:01 PM
                                  Not the same as 3-core CPU from a 4-core dieMark Roulo2022/07/04 09:31 AM
                                Wafer probingAdrian2022/07/05 03:08 AM
                                  Great comment, thank you (NT)anon22022/07/06 12:00 AM
                crystal latticehobold2022/06/27 12:09 PM
                  crystal latticedmcq2022/06/27 03:58 PM
                  Given path dependency I doubt it ...Mark Roulo2022/06/27 06:02 PM
                    Given path dependency I doubt it ...Adrian2022/06/27 10:01 PM
              Hexagonal DieMath Nerd2022/06/27 05:05 AM
                Hexagonal DieAdrian2022/06/27 10:24 PM
                  Hexagonal Diedmcq2022/07/06 03:00 PM
          Silicon ingots are round.dmcq2022/06/25 02:38 PM
            Silicon ingots are round.dmcq2022/06/25 02:43 PM
          Silicon ingots are round.aaron spink2022/06/25 03:05 PM
      Notch on Silicon WafersEric P2022/07/01 04:07 PM
        Still there, I think ...Mark Roulo2022/07/01 04:47 PM
          Still there, I think ...Eric P2022/07/01 05:26 PM
            Still there, I think ...tarlinian2022/07/01 06:50 PM
              Still there, I think ...David Kanter2022/07/02 09:14 AM
            Still there, I think ...Mark Roulo2022/07/01 09:31 PM
              Still there, I think ...Eric P2022/07/02 12:10 AM
  OK dumb question timeanonymouse2022/06/24 03:47 PM
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