Brett (ggtgp.delete@this.yahoo.com) on July 4, 2022 12:45 am wrote:
> anon2 (anon.delete@this.anon.com) on July 3, 2022 11:33 pm wrote:
> > Adrian (a.delete@this.acm.org) on July 3, 2022 10:25 pm wrote:
> > > Brett (ggtgp.delete@this.yahoo.com) on July 3, 2022 12:31 am wrote:
> > > > Mark Roulo (nothanks.delete@this.xxx.com) on July 2, 2022 4:41 pm wrote:
> > > > > Brett (ggtgp.delete@this.yahoo.com) on July 2, 2022 2:35 pm wrote:
> > > > > > Math Nerd (math.nerd.delete@this.nerds.com) on July 1, 2022 9:20 pm wrote:
> > > > > > > > triangles are better than rectangular or hexagonal dies at minimizing wasted area, and much easier to prove.
> > > > > > >
> > > > > > > Can someone please explain why triangular die are better than
> > > > > > > hexagonal die at minimizing wasted area on circular wafers?
> > > > > > >
> > > > > > > To be a fair comparison, the die of different shapes would have to have the same area because smaller
> > > > > > > die would certainly waste less area than larger die, regardless of shape. A hexagon with the same
> > > > > > > area as an equilateral triangle has about .8 the height and .8 the width of the equilateral triangle.
> > > > > > > A hexagon with the same area as an isosceles right triangle has about .8 the height and .9 the
> > > > > > > width of the isosceles right triangle. This smaller height and width allows the hexagon to get
> > > > > > > closer to the edge of a circle without going outside, which reduces wasted area.
> > > > > > >
> > > > > > > An advantage of isosceles right triangular die is that when near the edge of the circle, if
> > > > > > > two of them (forming a square) had one corner of the square outside the circle, a single triangle
> > > > > > > could be used there. A disadvantage of isosceles right triangular die, as mentioned earlier,
> > > > > > > is that they have a bigger width and height than hexagonal die of the same area.
> > > > > > >
> > > > > > > For triangular die, the wafer would need to be rotated in the lithography machine (stepper) or there would
> > > > > > > need to be multiple different versions of the same design
> > > > > > > on the mask. For equilateral triangles, about half
> > > > > > > the triangles would be printed with the vertex pointing
> > > > > > > up and the other half would be printed with the vertex
> > > > > > > pointing down. For right triangular die, 4 different directions of the hypotenuse would need to be printed
> > > > > > > to minimize wasted area. The hypotenuse direction needed
> > > > > > > on the left edge of the wafer is different from the
> > > > > > > hypotenuse direction needed on the right edge of the wafer
> > > > > > > and same for top vs bottom. A more practical problem
> > > > > > > with triangular die, pointed out by Adrian, is the difficulty of routing wires in the corners.
> > > > > > >
> > > > > > > The reason I suspect hexagonal die waste less area than rectangular die is that when rectangular die are
> > > > > > > trying to match an angle other than horizontal or vertical, there are big stair steps of wasted area. With
> > > > > > > hexagonal and equilateral triangular die, there are 4 angled directions (corresponding to perpendicular
> > > > > > > axes rotated 60 degrees) where the wasted area of stair steps is smaller than for rectangular die.
> > > > > >
> > > > > > As most CPU’s have two or more memory busses if you spread all your connections
> > > > > > on both half’s of the die you can salvage most of the dies on the edge.
> > > > > >
> > > > > > Since you have to put a pattern on the full wafer so polishing works evenly you have some CPU dies that are
> > > > > > more than half off the wafer, and many of those will work
> > > > > > in a reduced mode if you are smart in your layout.
> > > > > > If only two cores of 8 work, fine, sell it in the low end
> > > > > > laptop market, it was a one third sized die anyway.
> > > > >
> > > > > I think this would require non-trivial changes to the way the dies are laid out.
> > > > >
> > > > >
> > > > >
> > > > > Notice the IGPU on one end, the memory controller on the other and the ring bus in the middle?
> > > >
> > > > Yes, this die shot proves my point, 1/5th of the die is graphics, and many motherboards include
> > > > NVidea chips. Next to go is the small deactivated Gracemont cores, followed by the ring bus turning
> > > > into just a bus, which is not a big deal. Then you start dropping real CPU cores.
> > > >
> > > > Go find the pinout and you can find out how much of the die can die. ;)
> > > > By the picture I would rate 2/3rds can be missing and/or failed due to edge effects.
> > > > The pinout is probably more like half. Note that the upper layers wired to pins use
> > > > large transistors and wires and are not as seriously effected by edge effects.
> > > >
> > > > For Apple half the die is graphics and Apple can use a half failed
> > > > graphics unit in the iPhone mini or tablet mini or Apple TV.
> > > >
> > > > > I'm not claiming that this couldn't be done, but it won't be done trivially. The most straightforward way
> > > > > to do this is to go to chiplets, but even the AMD chiplets come with eight cores in a core complex.
> > > > >
> > > > > The chips on the edge of the wafer are the ones that have lower yield, too, so that adds another negative
> > > > > because you won't save as many partials as you might expect just looking at average yield per wafer.
> > > >
> > > >
> > >
> > >
> > > It should be noted that if a part of the designed die falls outside the wafer, estimating
> > > what blocks will not work is not as simple as looking were the wafer edge cuts the die.
> > >
> > > Around the die, there are normally passivation structures on the surface, to prevent surface
> > > leakage and electrical breakdown during operation, and also to prevent chemical contamination
> > > after the dies will be separated, e.g. trenches filled with special dielectrics.
> > >
> > > If the passivation structures are interrupted by the wafer edge, their protective effect would be lost
> > > and some other functional blocks inside the die might fail to work up to a long distance from the edge,
> > > or even the entire die could be destructed when the power supply will be connected for the first time.
> > >
> > >
> > > One could design a die to work partially even if the wafer edge falls over it, e.g. by adding extra
> > > passivation structures around the internal functional blocks, but that would increase the die area.
> > >
> > > Increasing the cost of all dies, for the dubious objective of getting a little higher yields by
> > > salvaging a few low-quality dies around the periphery of the wafer does not seem worthwhile.
> > >
> > > It could make sense only for extremely large dies, for which only a small number
> > > of dies could be obtained from a wafer, e.g. less than 100 dies per wafer.
> >
> > I'm not a mfg or packaging person but all of this would absolutely wreak havoc on wafer probing
> > as well as all the mechanical handling and mounting problems post-slicing, not to mention
> > an explosion of testing, binning, and supply chain issues with more part numbers.
> >
> > So before even worrying about laying out dies to optimize this
> > kind of edge yield, it's likely a non-starter from the get go.
>
> How hard is it to align three edges of a die instead of four for testing and packaging?

Well it would be at most 2 complete edges for any given partial die, wouldn't it? And almost all of them different around every part of the circle? Do have any idea what wafer and die testing and packaging and binning processes are like?

What are the mechanical and thermal properties and problems when you don't have a rectangular die? How about all your packaging steps? How will your heat spreader and heat sink clamping mechanically work? Do you need to have a different analysis and testing regime for every partial die shape? Do you need to develop and validate DVFS and other firmware tables for each partial configuration?

It's not going to be a matter of someone having a bright idea and whipping up a solution in a couple weeks, maybe write a few lines of code or adjust a few screws in a machine. It would be a big expensive long process, every die handling tool and step redesigned and even once the development and standardization costs were done, and this taken up by all your upstream and downstream partners. There will be a permanent variable cost imposed in expansion of test matrix / binning, and part numbers.

If it hasn't been done before on a commercial scale then it's not because they're all complete idiots and nobody thought of such a crude way to improve wafer usage, it is because it is not cost effective. So has it been done before?