Wafer probing

By: Adrian (a.delete@this.acm.org), July 5, 2022 3:08 am
Room: Moderated Discussions
anon2 (anon.delete@this.anon.com) on July 3, 2022 11:33 pm wrote:
> Adrian (a.delete@this.acm.org) on July 3, 2022 10:25 pm wrote:
> >
> > It could make sense only for extremely large dies, for which only a small number
> > of dies could be obtained from a wafer, e.g. less than 100 dies per wafer.
>
> I'm not a mfg or packaging person but all of this would absolutely wreak havoc on wafer probing
> as well as all the mechanical handling and mounting problems post-slicing, not to mention
> an explosion of testing, binning, and supply chain issues with more part numbers.
>
> So before even worrying about laying out dies to optimize this
> kind of edge yield, it's likely a non-starter from the get go.


You are of course right, but I want to comment about wafer probing.


A very large number of years ago, while working in a semiconductor plant, I have written some software for a wafer prober. Obviously some decades ago, and in a much smaller manufacturer than Intel or TSMC, the equipment was much less complex than today.

The wafer prober tests each die on a wafer before the final assembly and it marks the defective dies so that they will be separated after slicing the wafer and before assembly. It also gathers statistics about the wafer, e.g. which are the yields for quality classes, e.g. how many 5.0 GHZ CPUs will be made of it, how many 4.9 GHz, how many 4.8 GHz, how many with 6 cores, how many with 4 cores, and so on.

When the customer demand is not very large, wafers can be stored and assembled later only when there are orders for them. In that case the wafers sent to assembly are selected from storage depending on their bin proportions, so that the orders will be satisfied without assembling many undesired SKUs.


That wafer prober had a set of metallic needles that had to be pressed to contact test pads on the die. Before pressing down, the probing head had to be moved to the correct coordinates of a die on the wafer. The wafer was held on a vacuum chuck, but when the wafer was taken from the carrier and put on the chuck, the positioning was not accurate enough to know where the dies were in the coordinate system of the wafer prober.

Nowadays the wafer probers must have much more complex automated systems for alignment and positioning, but at that time, the simplest method for me was to detect the position of the wafer edge on the chuck, using a touch sensor, which could be lowered and which sensed the contact with the wafer.

Using the touch sensor, before probing any wafer, I sensed all around the circumference of the wafer, determining the edge position. Using the measured coordinates of the wafer edge, the coordinates of the wafer center and the inclination of the wafer flat (which was a part of the edge), could be computed, and from those, the coordinates of the dies.


After this explanation of the context, I reach to what I wanted to say about wafer probing. At that semiconductor plant, the equipment was mostly older, so it was not infrequent to have wafers that were accidentally broken at some process step.

When the broken part was not large and the breaking happened during the later phases of the manufacturing process, the broken wafer could usually complete all the process steps.

However the broken wafers created problems at wafer probing and they were previously aligned only manually for each die, which was very time consuming. The new wafer position detecting algorithm, which sensed the complete wafer edge, including any irregular parts caused by breakage, allowed the computation of the coordinates of all dies that were completely inside the non-broken part of the wafer, so that the wafer prober went only to the complete dies, to test them, and it ignored those damaged by breakage.


With modern wafer probers, which use video cameras and image processing, it should be even easier to determine which dies can be probed and tested, even if they are partial dies (if they had been designed to be functional even as a sub-die).


Nevertheless, as you have said , this is certainly much more trouble than a very small improvement in yields can justify.



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TopicPosted ByDate
OK dumb question timeDoug S2022/06/24 01:31 PM
  OK dumb question timeanon52022/06/24 01:38 PM
  Silicon ingots are round.Mark Roulo2022/06/24 02:29 PM
    Silicon ingots are round.Squarehead2022/06/24 02:38 PM
      Silicon ingots are round.Mark2022/06/24 03:00 PM
        Silicon ingots are round.Gary Kopp2022/06/24 03:20 PM
      Silicon ingots are round.Adrian2022/06/24 11:34 PM
    Silicon ingots are round.tarlinian2022/06/24 03:38 PM
      Silicon ingots are round.Doug S2022/06/24 11:13 PM
        Silicon ingots are round.anon2022/06/25 11:34 AM
          Silicon ingots are round.Doug S2022/06/25 11:39 AM
            Silicon ingots are round.Groo2022/06/26 09:41 AM
              Silicon ingots are round.Doug S2022/06/26 12:05 PM
                Silicon ingots are round.Gtoo2022/06/26 02:55 PM
          Silicon ingots are round.rwessel2022/06/25 11:43 AM
            Not reallyGroo2022/06/26 09:39 AM
              Not reallydmcq2022/06/26 10:56 AM
                Not reallyGroo2022/06/26 02:58 PM
              Not reallyanon22022/06/26 05:22 PM
              Why not triangles? Anon2022/06/27 03:34 AM
                Why not triangles? Math Nerd2022/06/27 04:52 AM
                Why not triangles? Math Nerd2022/06/27 05:45 AM
                  Don't forget Penrose Tiling (NT)ananon2022/06/27 06:06 AM
                  Why not triangles? Doug S2022/06/27 07:43 AM
                  Why not triangles? Anon2022/06/27 08:33 AM
                    Die shape that minimizes wasted area on circular wafersMath Nerd2022/07/01 09:20 PM
                      Die shape that minimizes wasted area on circular wafersBrett2022/07/02 02:35 PM
                        Die shape that minimizes wasted area on circular wafersMath Nerd2022/07/02 04:15 PM
                        Die shape that minimizes wasted area on circular wafersMark Roulo2022/07/02 04:41 PM
                          Die shape that minimizes wasted area on circular wafersDoug S2022/07/02 06:44 PM
                          Die shape that minimizes wasted area on circular wafersBrett2022/07/03 12:31 AM
                            Die shape that minimizes wasted area on circular wafersAdrian2022/07/03 10:25 PM
                              Die shape that minimizes wasted area on circular wafersanon22022/07/03 11:33 PM
                                Die shape that minimizes wasted area on circular wafersBrett2022/07/04 12:45 AM
                                  Die shape that minimizes wasted area on circular wafersdmcq2022/07/04 06:09 AM
                                    Die shape that minimizes wasted area on circular wafersJames2022/07/04 09:52 AM
                                      Die shape that minimizes wasted area on circular wafersdmcq2022/07/04 10:26 AM
                                        Die shape that minimizes wasted area on circular wafersAdrian2022/07/05 03:28 AM
                                      Cannon Lake vs Kaby LakeMark Roulo2022/07/04 10:30 AM
                                        C-class bonusesblue2022/07/04 12:27 PM
                                          C-class bonusesanonymou52022/07/04 03:23 PM
                                  Die shape that minimizes wasted area on circular wafersanon22022/07/04 06:53 AM
                                    Die shape that minimizes wasted area on circular wafersBrett2022/07/04 12:32 PM
                                      Die shape that minimizes wasted area on circular wafersFoyle2022/07/04 01:30 PM
                                        Die shape that minimizes wasted area on circular wafersAnon2022/07/04 01:37 PM
                                          What is a mirrored die?Mark Roulo2022/07/04 02:59 PM
                                            What is a mirrored die?Brett2022/07/04 03:32 PM
                                              What is a mirrored die?Doug S2022/07/04 10:08 PM
                                        Die shape that minimizes wasted area on circular wafersanonymou52022/07/04 03:12 PM
                                          Die shape that minimizes wasted area on circular wafersFoyle2022/07/05 10:41 AM
                                      Die shape that minimizes wasted area on circular wafersanon22022/07/04 04:52 PM
                                        Die shape that minimizes wasted area on circular wafersUngo2022/07/05 06:24 PM
                                          Die shape that minimizes wasted area on circular wafersBrett2022/07/05 07:56 PM
                                            Die shape that minimizes wasted area on circular wafersanonymou52022/07/06 05:46 AM
                                              Die shape that minimizes wasted area on circular wafersdmcq2022/07/06 02:55 PM
                                                Die shape that minimizes wasted area on circular wafersMark Roulo2022/07/06 04:09 PM
                                                Die shape that minimizes wasted area on circular wafersDoug S2022/07/06 05:31 PM
                                      Example of mirrored wafer?Mark Roulo2022/07/04 06:01 PM
                                  Not the same as 3-core CPU from a 4-core dieMark Roulo2022/07/04 09:31 AM
                                Wafer probingAdrian2022/07/05 03:08 AM
                                  Great comment, thank you (NT)anon22022/07/06 12:00 AM
                crystal latticehobold2022/06/27 12:09 PM
                  crystal latticedmcq2022/06/27 03:58 PM
                  Given path dependency I doubt it ...Mark Roulo2022/06/27 06:02 PM
                    Given path dependency I doubt it ...Adrian2022/06/27 10:01 PM
              Hexagonal DieMath Nerd2022/06/27 05:05 AM
                Hexagonal DieAdrian2022/06/27 10:24 PM
                  Hexagonal Diedmcq2022/07/06 03:00 PM
          Silicon ingots are round.dmcq2022/06/25 02:38 PM
            Silicon ingots are round.dmcq2022/06/25 02:43 PM
          Silicon ingots are round.aaron spink2022/06/25 03:05 PM
      Notch on Silicon WafersEric P2022/07/01 04:07 PM
        Still there, I think ...Mark Roulo2022/07/01 04:47 PM
          Still there, I think ...Eric P2022/07/01 05:26 PM
            Still there, I think ...tarlinian2022/07/01 06:50 PM
              Still there, I think ...David Kanter2022/07/02 09:14 AM
            Still there, I think ...Mark Roulo2022/07/01 09:31 PM
              Still there, I think ...Eric P2022/07/02 12:10 AM
  OK dumb question timeanonymouse2022/06/24 03:47 PM
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