By: zArchJon (anon.delete@this.anon.com), July 19, 2022 11:51 am
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on July 19, 2022 4:57 am wrote:
>
> One of the more surprising facts, which has been published by Intel only last year (without details),
> several years after being implemented in many CPUs, and of which I was not aware, is that there is
> a feature of Intel SGX, named XuCode, which allows an instruction to initiate not only the execution
> of a microprogram, as in CPUs without SGX, to alter the instruction behavior, but also the execution
> of an entire executable file, which is hidden inside the microcode update, as an ELF file.
>
> When executing XuCode, the Intel CPU is in a special mode, where only a subset of the
> x86-64 ISA is recognized, but there are available additional instructions and MSRs.
>
> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/secure-coding/xucode-implementing-complex-instruction-flows.html
>
>
The XuCode seems to be very much like the millicode that runs on IBM Z.
>
> One of the more surprising facts, which has been published by Intel only last year (without details),
> several years after being implemented in many CPUs, and of which I was not aware, is that there is
> a feature of Intel SGX, named XuCode, which allows an instruction to initiate not only the execution
> of a microprogram, as in CPUs without SGX, to alter the instruction behavior, but also the execution
> of an entire executable file, which is hidden inside the microcode update, as an ELF file.
>
> When executing XuCode, the Intel CPU is in a special mode, where only a subset of the
> x86-64 ISA is recognized, but there are available additional instructions and MSRs.
>
> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/secure-coding/xucode-implementing-complex-instruction-flows.html
>
>
The XuCode seems to be very much like the millicode that runs on IBM Z.
| Topic | Posted By | Date |
|---|---|---|
| Microinstruction format in older Atom CPUs | Adrian | 2022/07/19 04:57 AM |
| Microinstruction format in older Atom CPUs | zArchJon | 2022/07/19 11:51 AM |
| Microinstruction format in older Atom CPUs | dmcq | 2022/07/20 05:58 AM |
| Microinstruction format in older Atom CPUs | Linus Torvalds | 2022/07/19 01:29 PM |
| Microinstruction format in older Atom CPUs | Adrian | 2022/07/19 10:16 PM |
