IBM 5 bit microcontroller

By: Duane Sand (, July 30, 2022 3:44 pm
Room: Moderated Discussions
Paul Bishop ( on July 28, 2022 12:45 pm wrote:
> Yeah, nothing special. Just enough power to do it's job(s); 3033 power sequencing and control,
> 3033 control storage load, trace, metering, management. Wish I still had the complete set of
> ALDs for the 3033 and the latest 3036 diskettes with the 3033 control store load - although
> the docs had the complete control storage micro-program laid out in an automated ALD-like flowchart.
> Cool machine for its time. Last machine you could actually scope. If I can find the ALDs (paper
> or fische) I want to reproduce the machine in FPG(s) - minus the directors.

Thanks Paul, and also my thanks to 3036 programmer Joe Gosselin on Facebook, and emails with IBM hardware designer Bob Feretich.

The "5 bit engine" service processor (SVP) inside the 3036 operator and maintenance console desk was a simple 9.5MHz controller using 303X cache sram chips as its 10-bit-word memory. Instructions were 10 or 20 bits long. Registers and ALU and load-store operands were 5 bit bytes. The cache chips used were 11 bits wide, for 10 bits of code or data plus one parity bit. In the associated mainframes, I think 3 of these were used in parallel to form 32 data bits plus 1 data bit. The LSI gate array logic chips used and packaging were similar to those used in those mainframes, but air cooled. The controller's instruction cycle was matched 1:1 to the sram cycle rate. It was not microprogrammed. The cycle rate was fast for its time. I don't know what cycles/instruction was typical. The SVP's sram also held the display's screen text buffer and font tables.

The 9.5MHz rate quoted by Paul happens to be exactly 4 times the rate of IBM 3270's comm line bitrate. The SVP could be optionally used with remote displays in other rooms.

The SVP ISA grew from a risc-like load/store IBM controller project named Proteus. Proteus had no ALU, just an incrementor/decrementor circuit. Loops and counters relied on a curious "Fetch Increment" or "Fetch Decrement" instruction. It was like a load-immediate, except the value was incremented or decremented before getting latched into the visible register. A subsequent plain store instruction then inserted that revised value back into the Fetch Increment/Decrement instruction in memory. The immediate field of the instruction served as the variable's home location. When what you wanted was just a constant value N and not a counter, the instruction was assembled with value N-1.

The SVP inherited that curious instruction, but also had a longer reg-to-reg general ALU instruction, and picked the curious 5 bit width.

The 3036 SVP was first used in the 370 model 158, when IBM moved away from big panels of blinkenlights. Donald Hitt worked on that first version.

In the 3036 console used on 303X, there was two SVP processors and displays and floppy drives, mainly for fault tolerance. A working SVP was needed to boot up the mainframe with microcode from floppy. The two processors also allowed for managing job flow on one display while watching maintenance details on the other. A dual 3033 system had two 3036 desks with 4 displays, as the subsystems could run jointly or independently.

After the 303X timeframe and after the collapse of IBM's Future Systems effort, the 5-bit SVP engine was reimplemented as Advanced SVP with newer sram and hot dense logic chips. Bob Feretich did much of the hardware design. This was intended for supporting the 3090 mainframe. ASVP's lab prototype ran at 7nsec (projected) per instruction cycle, at twice the speed of the newer cache srams. It had prefetching from two interleaved banks of sram. The only pipe stalls were from branches and bank timing conflicts. The project had working chips but was canceled before custom Thermal Conduction Module wiring was manufactured. The on-time success of the 3080 project allowed more time for 3090 development. 3090 instead shipped with a competing IBM microcontroller chip called UC 1.0 (Universal Controller).

So yes, there was a 7nsec version of a simple 5 bit cpu at IBM.

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TopicPosted ByDate
IBM 5 bit microcontrollerDuane Sand2022/07/24 11:50 AM
  IBM 5 bit microcontrollerAdrian2022/07/24 09:53 PM
    IBM 5 bit microcontrollerAdrian2022/07/24 10:07 PM
      IBM 5 bit microcontrollerDuane Sand2022/07/24 11:39 PM
        IBM 5 bit microcontrollerAdrian2022/07/25 12:39 AM
  IBM 5 bit microcontrollerMatt Sayler2022/07/26 11:57 AM
    IBM 5 bit microcontrollerDuane Sand2022/07/26 03:19 PM
      IBM 5 bit microcontrollerMark Roulo2022/07/26 05:44 PM
        IBM 5 bit microcontrollerPaul Bishop2022/07/27 02:48 PM
          IBM 5 bit microcontrollerPaul Bishop2022/07/27 03:32 PM
            IBM 5 bit microcontrollerDuane Sand2022/07/28 01:44 AM
              IBM 5 bit microcontrollerPaul Bishop2022/07/28 12:45 PM
                IBM 5 bit microcontrollerDuane Sand2022/07/30 03:44 PM
                  IBM 5 bit microcontrollerPaul Bishop2022/07/31 04:03 AM
                    IBM 5 bit microcontrollerDuane Sand2022/07/31 10:26 AM
                      IBM 5 bit microcontrollerPaul Bishop2022/07/31 04:08 PM
                        IBM 5 bit microcontrollerDuane Sand2022/08/01 01:20 AM
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