By: rwessel (rwessel.delete@this.yahoo.com), August 9, 2022 9:32 am
Room: Moderated Discussions
Mark Roulo (nothanks.delete@this.xxx.com) on August 9, 2022 8:41 am wrote:
> Björn Ragnar Björnsson (bjorn.ragnar.delete@this.gmail.com) on August 8, 2022 6:31 pm wrote:
> > When the 21264 came out some of the worst problems had been fixed, but it was too little too late to save
> > the patient. I like to think of the Alpha's failure as being to due to "political correctness".
>
> I don't think "political correctness" is quite right.
>
> It is relatively easy to add to an architecture but much harder to remove features/functionality.
>
> So Alpha could fix the lack of byte instructions by adding them to later versions of the architecture.
OTH, the excessively relaxed memory consistency model was pretty baked in, and a PITA forever.
> MIPS found it much more difficult to remove the branch delay slot (simplest would be to add
> a whole new branch instruction, which is horrible ... I don't know if MIPS did this).
MIPS32 added a second set of branch instructions without a delay slot.
>680x0
> couldn't really "fix" the plethora of addressing modes and difficulty in decoding instructions
> in parallel (because it was tough to *find* the next instruction).
It made things more difficult, but not impossible. Consider the variety of techniques that have been used on x86 to identify instruction boundaries. Storing some pre-decode bits in the L1I, for example.
> Björn Ragnar Björnsson (bjorn.ragnar.delete@this.gmail.com) on August 8, 2022 6:31 pm wrote:
> > When the 21264 came out some of the worst problems had been fixed, but it was too little too late to save
> > the patient. I like to think of the Alpha's failure as being to due to "political correctness".
>
> I don't think "political correctness" is quite right.
>
> It is relatively easy to add to an architecture but much harder to remove features/functionality.
>
> So Alpha could fix the lack of byte instructions by adding them to later versions of the architecture.
OTH, the excessively relaxed memory consistency model was pretty baked in, and a PITA forever.
> MIPS found it much more difficult to remove the branch delay slot (simplest would be to add
> a whole new branch instruction, which is horrible ... I don't know if MIPS did this).
MIPS32 added a second set of branch instructions without a delay slot.
>680x0
> couldn't really "fix" the plethora of addressing modes and difficulty in decoding instructions
> in parallel (because it was tough to *find* the next instruction).
It made things more difficult, but not impossible. Consider the variety of techniques that have been used on x86 to identify instruction boundaries. Storing some pre-decode bits in the L1I, for example.
