rwessel (rwessel.delete@this.yahoo.com) on August 10, 2022 11:48 am wrote:
> Mark Roulo (nothanks.delete@this.xxx.com) on August 10, 2022 9:34 am wrote:
> > Doug S (foo.delete@this.bar.bar) on August 10, 2022 9:09 am wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on August 10, 2022 6:54 am wrote:
> > > > Doug S (foo.delete@this.bar.bar) on August 9, 2022 9:19 pm wrote:
> > > > > Björn Ragnar Björnsson (bjorn.ragnar.delete@this.gmail.com) on August 9, 2022 2:36 pm wrote:
> > > > > > "Digital intended the architecture to support a one-thousandfold increase in performance
> > > > > > over twenty-five years. To ensure this, any architectural feature that impeded multiple
> > > > > > instruction issue, clock rate or multiprocessing was removed."
> > > > >
> > > > >
> > > > > That's a good thing though, in the long run. Because the
> > > > > whole industry benefits as much from seeing what NOT
> > > > > to do as seeing what to do. They took the RISC philosophy
> > > > > (which was married closely to the speed demon philosophy
> > > > > at the time) to its logical extreme, kind of like how Intel's 432 took CISC to its logical extreme.
> > > > >
> > > >
> > > > Out of Alpha 21064 approximate contemporaries, I would think about IBM ES/9000 (CISC) water-cooled
> > > > models as an ultimate Speed Demon and about IBM (also!) POWER2 (RISC) as an ultimate Brainiac.
> > >
> > >
> > > Was the ES/9000 really architected to be a "speed demon" or simply overengineered
> > > with features like water cooling and bipolar transistors?
> > >
> > > An Apple M2 made in a hypothetical modern equivalent of a bipolar process that allowed operating
> > > at much higher frequencies in exchange for much higher power draw, cooled with LN2 to keep it
> > > from melting, wouldn't be a speed demon no matter how high you were able to clock it.
> >
> > If by ES/9000 we mean the S/390 CPU (~1997) then I think speed demon is reasonable.
> > The S/390 CPU had many functional units, but dispatched only
> > one instruction per clock (according to the source
> > to which I have a link) while aiming for a high clock rate.
> > That seems speed-demony to me compared to, say,
>
>
> High clock rate, but only modestly OoO. At least a bit in the speed-demony direction, but not terribly in the
> mainstream of processor design. With limitations, it could decode and dispatch two instructions at a time.
>
> https://web.archive.org/web/20220125034326/https://pdf.zlibcdn.com/dtoken/22d21add4960740319abf78173c45b4d/rd.364.0713.pdf
>
> Note that "ES/9000" referred to a family of machines, known as the 9021, 9121 and 9221. Only the big ones
> (the 9021s) were OoO, and those were built with two different "cores" over time (the 511s and 711).
>
>
> > Pentium Pro which would issue up to three instructions per clock or the PA-7200 which could dispatch two.
> >
> > https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.15.1962&rep=rep1&type=pdf
> >
> > I think the next gen of IBM mainframe CPUs got wider.
>
>
> The IBM 9021s were the last of the bipolar machines (at least from IBM - Hitachi and Fujitsu
> held on a bit longer), and were replaced by later models of the CMOS (and microprocessor) 9672s*,
> but those were all in-order (later ones superscalar) until the z196**, if memory serves.
>
> *The 9672-G4s kinda matched the uniprocessor performance of the 9021-711s, but the
> systems were available with more cores. The G5s were solidly faster. The earlier
> 9672s were lower-end machines and for use with EP workloads in clusters.
>
> **Effectively the 9672-G11, although they renamed the line "Z" after the G6s. So the first Z,
> the z900, is effectively the 9672-G7, other than the z900s, z990 ("G8") and z196 ("G11"), they
> went back to reflecting the 9672 generation numbering (z9, z10, zEC12, z13, z14, z15, z16).

I'm surprised the IBM mainframes didn't do OoO more. The basic instructions look fairly easy to decode plus they've got essentially a large library of special things. I'd say they were more on the lines of what a RISC with a large expansion for the real world would look like. Perhaps there was a problem with their memory model they needed to work out?