Anon (no.delete@this.spam.com) on August 11, 2022 5:45 pm wrote:
> Brett (ggtgp.delete@this.yahoo.com) on August 11, 2022 3:26 pm wrote:
> > Anon (no.delete@this.spam.com) on August 11, 2022 11:43 am wrote:
> > > Megol (golem960.delete@this.gmail.com) on August 11, 2022 9:25 am wrote:
> > > > Have you actually looked at the 68080 design? The extensions aren't that clean, and for a good reason:
> > > > there isn't encoding space without adding prefixes or adding a partially incompatible mode.
> > >
> > > Where did you find the instruction format?
> >
> > Any 68k manual, each instruction spells out the bits:
> > https://web.njit.edu/~rosensta/classes/architecture/252software/code.pdf
> >
> > There is unused state in the mode bits that can be used to add another 8 data registers transparently for
> > one source. Though instead the AMMX extension added 32 bit instructions and used a similar format.
> >
> > https://cdn.discordapp.com/attachments/730698753513750539/843620828612526110/VampireProgrammingGuide.pdf#page55
> >
> > ColdFire obsoleted the 2 of the 3 opmode operation size bits for all but MOVE loads/stores. That frees up
> > huge opportunities for expansion. The plan may have been to use these bits to double the register file.
> >
> > http://bitsavers.org/components/motorola/Coldfire/1995_Coldfire_Family_Programmers_Reference.pdf
> >
> > Ugly, but not so ugly as x86.
>
> Thanks for posting links to manuals I already have without answearing my question, but what I really
> want is the actual basic instruction format for the 68080, and how it extended over 68060.


Maybe this?

https://github.com/mbitsnbites/vasm-mirror/blob/master/cpus/m68k/opcodes.h

I find text such as this:

"abcd", {D_,D_}, {{RLO,RHI}, {0xc100,0},1|B|S_NONE,m68000up},
"abcd", {PA,PA}, {{RLO,RHI}, {0xc108,0},1|B|S_NONE,m68000up},
"abs", {AY,R_}, {{SEA,C2H}, {0x0e00,0x0001},2|BWL|S_STD,apollo},
"abs", {AY,B_}, {{SEA,C2H}, {0x0e00,0x0081},2|BWL|S_STD,apollo},
"abs", {BY,R_}, {{SEA,C2H}, {0x0e00,0x0101},2|BWL|S_STD,apollo},
"abs", {BY,B_}, {{SEA,C2H}, {0x0e00,0x0181},2|BWL|S_STD,apollo},
"abs", {R_,NI}, {{C2H,SEA}, {0x0e00,0x0801},2|BWL|S_STD,apollo},
"abs", {B_,NI}, {{C2H,SEA}, {0x0e00,0x0881},2|BWL|S_STD,apollo},
"abs", {R_,BI}, {{C2H,SEA}, {0x0e00,0x0901},2|BWL|S_STD,apollo},
"abs", {B_,BI}, {{C2H,SEA}, {0x0e00,0x0981},2|BWL|S_STD,apollo},
"add", {DA,D_}, {{SEA,RHI}, {0xd000,0},1|CFBWL|S_STD,m68000up|mcf},
"add", {A_,D_}, {{SEA,RHI}, {0xd000,0},1|CFWL|S_STD,m68000up|mcf},
"add", {A_,D_}, {{SEA,RHI}, {0xd000,0},1|BWL|S_STD,apollo},

Note the "apollo" entries.