By: Anon (no.delete@this.spam.com), August 11, 2022 10:40 pm
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on August 11, 2022 11:10 pm wrote:
> The CPU's where the latency of register addition has been 2 or 0.5
> or other values different from 1 have been obsolete for decades.
Well, I mentioned them in the context of "IPC = 1" bullshit, but in fact, since ILP does exists lowering instruction latency isn't all that important.
> Now, already for a long time there has been a consensus that both superpipelined
> and underpipelined CPU's are worse than the CPU's where the latency of register
> addition is 1, so the latter is true for all modern CPU's.
True, but I think this may change in the future.
> The CPU's where the latency of register addition has been 2 or 0.5
> or other values different from 1 have been obsolete for decades.
Well, I mentioned them in the context of "IPC = 1" bullshit, but in fact, since ILP does exists lowering instruction latency isn't all that important.
> Now, already for a long time there has been a consensus that both superpipelined
> and underpipelined CPU's are worse than the CPU's where the latency of register
> addition is 1, so the latter is true for all modern CPU's.
True, but I think this may change in the future.
