Marcus (m.delete@this.bitsnbites.eu) on August 16, 2022 7:52 am wrote:
> I personally think that 64 GPR:s in a unified register file is overkill, as it's "more" than 32 scalar
> int + 32 scalar float registers ("more" because of the more dynamic register allocation opportunities
> - it's probably exceedingly rare with a perfect 50:50 mix of integer and float register pressure),
> so my guess is that the break-even is closer to 48 GPRs. Are there any papers on the subject?

Actually there are some papers, but, have you encountered a situation where 32 scalar registers aren't enough? From the papers I remember those situations are very rare.

> So, in MRISC32 I have 32 scalar GPRs (int+float), but on the other hand I also have 32
> vector registers

IIRC AMD RDNA does the same.

> I'm completely uncertain if this is a good model in wide OoO machines, but it works really
> well in my narrow in-order implementation, and it's a very nice software model.

I don't see why it wouldn't work on OoO. Actually OoO made terrible ISAs work.