Doug S (foo.delete@this.bar.bar) on July 30, 2022 10:43 pm wrote:
> David Hess (davidwhess.delete@this.gmail.com) on July 30, 2022 3:44 pm wrote:
> > David Hess (davidwhess.delete@this.gmail.com) on July 29, 2022 8:59 pm wrote:
> >
> > Last night I remembered another computer system which could start up exactly where it
> > left off after power loss; this was a feature of some systems which used core memory.
> > It was a small step from relying on core memory for program and data storage, to including
> > circuits to safely shut down and restart after power loss by saving CPU state.
> >
> > This could also have been done with a microprocessor and CMOS SRAM or even DRAM, but
> > I do not remember any systems which did it that way. Someone must have though.
>
> This is before my time but in the core memory days booting was kind of a pain
> in the ass, was it not? Even if you had the luxury of a hard drive you probably
> had to either toggle in a bootloader or load it via paper tape.
>
> That was probably the main reason that was used, not necessarily because they wanted to pick up where
> they left off - but if the PC, SP and registers were themselves stored in a type of core memory (or
> there was a big capacitor or something allowing a split second for them to be saved to core memory)
> then I guess theoretically it could simply pick up where it left off once power returns.

Core memory was contemporaneous with SRAM, DRAM, ROM, PROM, UVEPROM, and floppy disk storage. The oldest systems I worked on booted a monitor from UVEPROM which then booted from floppy disk, but embedded systems ran directly from UVEPROM. It was the mini-computers which commonly had core memory but they also booted from floppy disk or UVEPROM. Any combination was possible in an embedded system. Toggling in a bootloader was optional by then.

Low power CMOS SRAM suitable for battery backup did not exist yet though. It was sometimes done anyway with huge batteries to give only hours to days of backup time.

For an embedded system running from ROM and/or core memory, there was plenty of time after detecting loss of power to save the processor state, which is still the case today for many embedded systems. Back then it might be no more complicated than subroutine entry and exit.