By: Brett (ggtgp.delete@this.yahoo.com), August 7, 2022 5:37 pm
Room: Moderated Discussions
Anon (no.delete@this.spam.com) on August 7, 2022 2:57 pm wrote:
> Marcus (m.delete@this.bitsnbites.eu) on August 6, 2022 4:36 am wrote:
> > Have you seen the 68080? It's a 64-bit 4-wide OoO 68k CPU with more registers and instructions
> > than the 32-bit 68k line (68000-68060). It's implemented in an FPGA. Pretty impressive IMO.
> >
> > http://www.apollo-core.com/index.htm?page=coding&tl=1
> >
> > /Marcus
>
> I looked for but didn't found, what is the instruction format?
> I mean, how 68k was extended? Was it like x86 rex prefix?
Page 55, Detecting_AMMX_in_AmigaOS
https://cdn.discordapp.com/attachments/730698753513750539/843620828612526110/VampireProgrammingGuide.pdf#page55
Basically they filled out the addressing table adding 24 more data registers and 8 more address registers with limitations. They also added MMX style instructions for the data registers. All registers are 64 bit. Support for double indirect loads is not in the AMMX extension, a good choice.
As much as I once loved the 68000, it is a horrid kludge that was just thrown together without an understanding of software.
On paper it is close to my ideal of post RISC with 16 address/data registers plus 64 data/float/vector registers. Had Motorola been competent these additions would have happened decades ago and we would still be using these chips, despite the flaws. Much like x86.
> Marcus (m.delete@this.bitsnbites.eu) on August 6, 2022 4:36 am wrote:
> > Have you seen the 68080? It's a 64-bit 4-wide OoO 68k CPU with more registers and instructions
> > than the 32-bit 68k line (68000-68060). It's implemented in an FPGA. Pretty impressive IMO.
> >
> > http://www.apollo-core.com/index.htm?page=coding&tl=1
> >
> > /Marcus
>
> I looked for but didn't found, what is the instruction format?
> I mean, how 68k was extended? Was it like x86 rex prefix?
Page 55, Detecting_AMMX_in_AmigaOS
https://cdn.discordapp.com/attachments/730698753513750539/843620828612526110/VampireProgrammingGuide.pdf#page55
Basically they filled out the addressing table adding 24 more data registers and 8 more address registers with limitations. They also added MMX style instructions for the data registers. All registers are 64 bit. Support for double indirect loads is not in the AMMX extension, a good choice.
As much as I once loved the 68000, it is a horrid kludge that was just thrown together without an understanding of software.
On paper it is close to my ideal of post RISC with 16 address/data registers plus 64 data/float/vector registers. Had Motorola been competent these additions would have happened decades ago and we would still be using these chips, despite the flaws. Much like x86.
