Brett (ggtgp.delete@this.yahoo.com) on August 8, 2022 12:31 am wrote:
> Marcus (m.delete@this.bitsnbites.eu) on August 7, 2022 11:30 pm wrote:
> > Megol (golem960.delete@this.gmail.com) on August 7, 2022 2:01 pm wrote:
> > > Marcus (m.delete@this.bitsnbites.eu) on August 6, 2022 4:36 am wrote:
> > > > Have you seen the 68080? It's a 64-bit 4-wide OoO 68k CPU with more registers and instructions
> > > > than the 32-bit 68k line (68000-68060). It's implemented in an FPGA. Pretty impressive IMO.
> > >
> > > AFAIK it's an in-order 2 wide superscalar with load-execute-store pipelines and powerful instruction fusion?
> > > Personally the extensions are too hacky but yes, pretty impressive.
> > >
> >
> > I have trouble finding any definitive information and thorough documentation,
> > but check out http://www.apollo-core.com/index.htm?page=features
> >
> > It states:
> >
> > * Out of Order CPU
> > * Out of Order FPU
> > * Executes up to 4 instructions per clock cycle
> >
> > OTOH it only has two integer execution units, according to the same
> > page, so four instructions may be when mixing in FPU & AMMX?
>
> A typical 4 way RISC arch will have around two integer, a load pipe, a load/store pipe, FPU mul, FPU add.
> So up to six issue, but the decode and complete are four wide, determining width.

Do you have any information about the decode width of the 68080?

I would love to see an microarchitecture diagram (similar to those on wikichip).