By: Adrian (a.delete@this.acm.org), August 9, 2022 11:21 am
Room: Moderated Discussions
"AEPIC Leak is the first architectural CPU bug that leaks stale data from the microarchitecture without using a side channel. It architecturally leaks stale data incorrectly returned by reading undefined APIC-register ranges."
This hardware bug works against SGX on Ice Lake/Ice Lake Server/Alder Lake cores, presumably also on Tiger Lake/Rocket Lake.
I wonder if this is the bug that has been corrected in the latest version of Sapphire Rapids.
PoC code:
https://github.com/IAIK/AEPIC
Paper:
https://aepicleak.com/aepicleak.pdf
| Topic | Posted By | Date |
|---|---|---|
| AEPIC leak | Adrian | 2022/08/09 11:21 AM |
| AEPIC leak | Michael S | 2022/08/09 11:32 AM |
| AEPIC leak | rwessel | 2022/08/09 11:56 AM |
| AEPIC leak | hobold | 2022/08/09 12:20 PM |
