By: Anon (no.delete@this.spam.com), August 25, 2022 5:25 am
Room: Moderated Discussions
Etienne (etienne_lorrain.delete@this.yahoo.fr) on August 25, 2022 1:54 am wrote:
> Like "load cacheline on local L1 D-cache in exclusive mode and refuse to share that cacheline"?
> At some point your request has to be cancelled, else all processing
> may stop due to a bug or an AB - BA lockup by two cores.
> At that point (cancel exclusive request) you want an exception?
> I also imagine there would be a limit on the number of cachelines a core refuses to share...
I don't know, what I expect from a hardware claiming to provide transactions is that, when I request something within the predefined limits defined by the hardware vendor to be done atomically it will be done atomically, I know this is hard and the bigger the transaction the harder it will be, not everything in life is easy.
> Like "load cacheline on local L1 D-cache in exclusive mode and refuse to share that cacheline"?
> At some point your request has to be cancelled, else all processing
> may stop due to a bug or an AB - BA lockup by two cores.
> At that point (cancel exclusive request) you want an exception?
> I also imagine there would be a limit on the number of cachelines a core refuses to share...
I don't know, what I expect from a hardware claiming to provide transactions is that, when I request something within the predefined limits defined by the hardware vendor to be done atomically it will be done atomically, I know this is hard and the bigger the transaction the harder it will be, not everything in life is easy.