Hardware Transactional Memory, the end?

By: rwessel (rwessel.delete@this.yahoo.com), August 25, 2022 8:16 am
Room: Moderated Discussions
Etienne (etienne_lorrain.delete@this.yahoo.fr) on August 25, 2022 6:24 am wrote:
> Anon (no.delete@this.spam.com) on August 25, 2022 5:25 am wrote:
> > Etienne (etienne_lorrain.delete@this.yahoo.fr) on August 25, 2022 1:54 am wrote:
> > > Like "load cacheline on local L1 D-cache in exclusive mode and refuse to share that cacheline"?
> > > At some point your request has to be cancelled, else all processing
> > > may stop due to a bug or an AB - BA lockup by two cores.
> > > At that point (cancel exclusive request) you want an exception?
> > > I also imagine there would be a limit on the number of cachelines a core refuses to share...
> >
> > I don't know, what I expect from a hardware claiming to
> > provide transactions is that, when I request something
> > within the predefined limits defined by the hardware vendor
> > to be done atomically it will be done atomically,
> > I know this is hard and the bigger the transaction the harder it will be, not everything in life is easy.
> >
>
> Maybe an interface like "mwait" but waiting that a (finite) list of data cachelines
> (and few code cacheline covering code to be executed) are all available in exclusive
> mode on the local core would be better then, probably with a timeout.
> You would not be sure that such "wait" ever succeed without timeout, but if it does then
> the transaction can start and will complete... unless you use absent cachelines.
> Not sure how easy to implement in hardware, not sure how easy to use in software.
> At least it would not waste resources, and the sibling core would have time to do its stuff.


I'm not sure I understand this concern. The transaction appears (eventually) to all other cores as a single atomic event. In practice another transaction (or a non-transactional access) can interfere, and prevent completion, but they can't cause a deadlock. Worst case a "guaranteed" transaction eventually halts all other cores in the configuration while doing a couple of retries (one would hope that such an extreme measure would be quite rare, but it's a plausible last resort). Even a normal (non-guaranteed) transaction can use random backoff to increase the odds of success.
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TopicPosted ByDate
Hardware Transactional Memory, the end?rwessel2022/08/20 06:50 PM
  Hardware Transactional Memory, the end?Kara2022/08/20 11:04 PM
    Hardware Transactional Memory, the end?dmcq2022/08/21 11:36 AM
      Hardware Transactional Memory, the end?rwessel2022/08/21 12:17 PM
        Hardware Transactional Memory, the end?---2022/08/21 01:26 PM
          Hardware Transactional Memory, the end?Andrey2022/08/21 06:39 PM
            Hardware Transactional Memory, the end?---2022/08/21 09:27 PM
              Hardware Transactional Memory, the end?Andrey2022/08/23 06:29 AM
                Hardware Transactional Memory, the end?---2022/08/23 10:00 AM
                  Hardware Transactional Memory, the end?iz2022/08/23 01:20 PM
                    Hardware Transactional Memory, the end?anonymou52022/08/23 02:57 PM
                  Hardware Transactional Memory, the end?Andrey2022/08/23 06:01 PM
                    Hardware Transactional Memory, the end?Anon2022/08/23 06:28 PM
                      Hardware Transactional Memory, the end?Andrey2022/08/24 04:10 AM
                        Hardware Transactional Memory, the end?Anon2022/08/24 08:50 AM
                          Hardware Transactional Memory, the end?rwessel2022/08/24 09:35 AM
                          Hardware Transactional Memory, the end?Etienne2022/08/25 01:54 AM
                            Hardware Transactional Memory, the end?Anon2022/08/25 05:25 AM
                              Hardware Transactional Memory, the end?Etienne2022/08/25 06:24 AM
                                Hardware Transactional Memory, the end?rwessel2022/08/25 08:16 AM
                                  Hardware Transactional Memory, the end?Linus Torvalds2022/08/25 10:16 AM
                                    Hardware Transactional Memory, the end?rwessel2022/08/25 11:00 AM
                                  Hardware Transactional Memory, the end?Etienne2022/08/26 12:54 PM
                    Hardware Transactional Memory, the end?anon22022/08/23 08:50 PM
                      Hardware Transactional Memory, the end?Andrey2022/08/24 03:54 AM
                        Hardware Transactional Memory, the end?anon22022/08/24 04:54 AM
                      Hardware Transactional Memory, the end?Simon Farnsworth2022/08/24 03:58 AM
                        Hardware Transactional Memory, the end?Konrad Schwarz2022/08/28 06:12 AM
          Hardware Transactional Memory, the end?Linus Torvalds2022/08/21 06:58 PM
            Hardware Transactional Memory, the end?rwessel2022/08/21 08:02 PM
              Hardware Transactional Memory, the end?anon22022/08/21 09:31 PM
                Hardware Transactional Memory, the end?dmcq2022/08/22 07:14 AM
                  Hardware Transactional Memory, the end?anon22022/08/23 12:15 AM
                    Hardware Transactional Memory, the end?dmcq2022/08/24 03:50 AM
                      Hardware Transactional Memory, the end?Linus Torvalds2022/08/24 11:56 AM
                        Hardware Transactional Memory, the end?dmcq2022/08/25 04:39 PM
            Hardware Transactional Memory, the end?---2022/08/21 09:33 PM
              Hardware Transactional Memory, the end?Linus Torvalds2022/08/22 11:32 AM
                Hardware Transactional Memory, the end?Anon2022/08/22 12:35 PM
                  Hardware Transactional Memory, the end?rwessel2022/08/22 04:47 PM
                Hardware Transactional Memory, the end?gpd2022/08/26 03:07 AM
                  Hardware Transactional Memory, the end?Michael S2022/08/26 03:46 AM
                    Hardware Transactional Memory, the end?Linus Torvalds2022/08/26 11:01 AM
                      Hardware Transactional Memory, the end?rwessel2022/08/26 06:08 PM
                        Hardware Transactional Memory, the end?anonymou52022/08/26 07:52 PM
  Hardware Transactional Memory, the end?zArchJon2022/08/24 10:12 AM
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