By: Michael S (already5chosen.delete@this.yahoo.com), August 26, 2022 3:46 am
Room: Moderated Discussions
gpd (gpderetta.delete@this.gmail.com) on August 26, 2022 3:07 am wrote:
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on August 22, 2022 11:32 am wrote:
> > --- (---.delete@this.redheron.com) on August 21, 2022 9:33 pm wrote:
> > >
> > > Just so I understand, Linus, are you saying that
> > > (a) You NEED LL4/SC4 for correctness? That is, if you can trust LL4/SC4 to do what's promised, various
> > > constructions that today are very messy/finicky/slow can be replaced with something much simpler
> >
> > No, I most certainly don't "need" it.
> >
>
> Around 10 years ago AMD proposed exactly your design: guaranteed
> forward progress transactions to up to 4 cachelines:
> http://developer.amd.com/wordpress/media/2013/09/45432-ASF_Spec_2.1.pdf
>
> In the end of course it was never implemented, and I think the original spec actually guaranteed transactions
> to up to 7 cachelines as apparently that's enough for a lot of useful lock free algorithms.
>
>
I would guess that if we enumerate cases that are
A. Useful in parctice
B. Can not be done with 1 cache line
C. Can be done with unlimited number of distinct lines
then about half of them can be done with 2 distinct lines.
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on August 22, 2022 11:32 am wrote:
> > --- (---.delete@this.redheron.com) on August 21, 2022 9:33 pm wrote:
> > >
> > > Just so I understand, Linus, are you saying that
> > > (a) You NEED LL4/SC4 for correctness? That is, if you can trust LL4/SC4 to do what's promised, various
> > > constructions that today are very messy/finicky/slow can be replaced with something much simpler
> >
> > No, I most certainly don't "need" it.
> >
>
> Around 10 years ago AMD proposed exactly your design: guaranteed
> forward progress transactions to up to 4 cachelines:
> http://developer.amd.com/wordpress/media/2013/09/45432-ASF_Spec_2.1.pdf
>
> In the end of course it was never implemented, and I think the original spec actually guaranteed transactions
> to up to 7 cachelines as apparently that's enough for a lot of useful lock free algorithms.
>
>
I would guess that if we enumerate cases that are
A. Useful in parctice
B. Can not be done with 1 cache line
C. Can be done with unlimited number of distinct lines
then about half of them can be done with 2 distinct lines.