Hardware Transactional Memory, the end?

By: rwessel (rwessel.delete@this.yahoo.com), August 26, 2022 6:08 pm
Room: Moderated Discussions
Linus Torvalds (torvalds.delete@this.linux-foundation.org) on August 26, 2022 11:01 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on August 26, 2022 3:46 am wrote:
> >
> > I would guess that if we enumerate cases that are
> > A. Useful in parctice
> > B. Can not be done with 1 cache line
> > C. Can be done with unlimited number of distinct lines
> > then about half of them can be done with 2 distinct lines.
>
> No, I really do think that 3 distinct lines are pretty much required - since
> the most obvious case I can think of (doubly linked list) needs it.
>
> And yes, yes, if you look up DCAS and doubly linked lists, you'll find that people
> talk about just two lines for that operation - but that's not for a doubly linked list
> that is coherent with a lock, that's for a purely unlocked doubly linked list.
>
> In fact, I suspect that you actually really want four lines, because while three should be sufficient
> for a doubly linked list (modifying the two entries on both sides, and checking the lock), you probably
> do want to also hold/modify the cacheline of the entry itself that you are adding or removing.
>
> Yes, you can probably make do without that fourth entry - When adding an entry to the linked
> list you can pre-fill the prev/next pointers of the new entry before actually doing the operation
> - and that's the kinds of tricks that you have to do when you only have one entry and you
> are using 'cmpxchg' or 'll/sc' to do simpler lock-free singly-linked lists.
>
> But I do suspect that four cachelines is noticeably better than three,
> and two is just simply not sufficient for a lot of simple things.
>
> That said, even just two is probably usable for some things. People who implement locking
> would use it internally, I bet, and it might be sufficient for a number of "test condition
> consistent with a lock" situations. I just think that "doubly linked list handling co-existing
> with a lock" is probably worth considering as a minimally useful thing.
>
> I dunno.
>
> I suspect in the end it's one of those things where it's just not
> useful enough: locking works, and usually works well enough.


FWIW, Z Perform Locked Operation supports up to compare-and-swap-and-triple-store, but keeps the lock itself separately. So roughly four the way you're counting.
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TopicPosted ByDate
Hardware Transactional Memory, the end?rwessel2022/08/20 06:50 PM
  Hardware Transactional Memory, the end?Kara2022/08/20 11:04 PM
    Hardware Transactional Memory, the end?dmcq2022/08/21 11:36 AM
      Hardware Transactional Memory, the end?rwessel2022/08/21 12:17 PM
        Hardware Transactional Memory, the end?---2022/08/21 01:26 PM
          Hardware Transactional Memory, the end?Andrey2022/08/21 06:39 PM
            Hardware Transactional Memory, the end?---2022/08/21 09:27 PM
              Hardware Transactional Memory, the end?Andrey2022/08/23 06:29 AM
                Hardware Transactional Memory, the end?---2022/08/23 10:00 AM
                  Hardware Transactional Memory, the end?iz2022/08/23 01:20 PM
                    Hardware Transactional Memory, the end?anonymou52022/08/23 02:57 PM
                  Hardware Transactional Memory, the end?Andrey2022/08/23 06:01 PM
                    Hardware Transactional Memory, the end?Anon2022/08/23 06:28 PM
                      Hardware Transactional Memory, the end?Andrey2022/08/24 04:10 AM
                        Hardware Transactional Memory, the end?Anon2022/08/24 08:50 AM
                          Hardware Transactional Memory, the end?rwessel2022/08/24 09:35 AM
                          Hardware Transactional Memory, the end?Etienne2022/08/25 01:54 AM
                            Hardware Transactional Memory, the end?Anon2022/08/25 05:25 AM
                              Hardware Transactional Memory, the end?Etienne2022/08/25 06:24 AM
                                Hardware Transactional Memory, the end?rwessel2022/08/25 08:16 AM
                                  Hardware Transactional Memory, the end?Linus Torvalds2022/08/25 10:16 AM
                                    Hardware Transactional Memory, the end?rwessel2022/08/25 11:00 AM
                                  Hardware Transactional Memory, the end?Etienne2022/08/26 12:54 PM
                    Hardware Transactional Memory, the end?anon22022/08/23 08:50 PM
                      Hardware Transactional Memory, the end?Andrey2022/08/24 03:54 AM
                        Hardware Transactional Memory, the end?anon22022/08/24 04:54 AM
                      Hardware Transactional Memory, the end?Simon Farnsworth2022/08/24 03:58 AM
                        Hardware Transactional Memory, the end?Konrad Schwarz2022/08/28 06:12 AM
          Hardware Transactional Memory, the end?Linus Torvalds2022/08/21 06:58 PM
            Hardware Transactional Memory, the end?rwessel2022/08/21 08:02 PM
              Hardware Transactional Memory, the end?anon22022/08/21 09:31 PM
                Hardware Transactional Memory, the end?dmcq2022/08/22 07:14 AM
                  Hardware Transactional Memory, the end?anon22022/08/23 12:15 AM
                    Hardware Transactional Memory, the end?dmcq2022/08/24 03:50 AM
                      Hardware Transactional Memory, the end?Linus Torvalds2022/08/24 11:56 AM
                        Hardware Transactional Memory, the end?dmcq2022/08/25 04:39 PM
            Hardware Transactional Memory, the end?---2022/08/21 09:33 PM
              Hardware Transactional Memory, the end?Linus Torvalds2022/08/22 11:32 AM
                Hardware Transactional Memory, the end?Anon2022/08/22 12:35 PM
                  Hardware Transactional Memory, the end?rwessel2022/08/22 04:47 PM
                Hardware Transactional Memory, the end?gpd2022/08/26 03:07 AM
                  Hardware Transactional Memory, the end?Michael S2022/08/26 03:46 AM
                    Hardware Transactional Memory, the end?Linus Torvalds2022/08/26 11:01 AM
                      Hardware Transactional Memory, the end?rwessel2022/08/26 06:08 PM
                        Hardware Transactional Memory, the end?anonymou52022/08/26 07:52 PM
  Hardware Transactional Memory, the end?zArchJon2022/08/24 10:12 AM
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