Rayla (rayla.delete@this.example.com) on August 27, 2022 12:04 pm wrote:
> Kara (karaardalan.delete@this.gmail.com) on August 27, 2022 11:21 am wrote:
> > Rayla (rayla.delete@this.example.com) on August 27, 2022 10:35 am wrote:
> > > and a memory interface far slower than those present in GPUs in a similar FLOPS range
> >
> > You know it's ddr5 right? 32-channel ddr5
>
> Yes. I think I'm somewhat less impressed by 900GB/s than you are, considering it's competing with GPUs that
> do numbers in the multi-TB/s range and still hit bandwidth limitations. But I've also come to the conclusion
> that you have unconventional views on semiconductor design and that we're unlikely to agree on much.

Although the system memory bandwidth for high-spec Tachyum is greater
than the upcoming EPYC Genoa, the per core bandwidth is essentially the
same. Additionally the Tachyum is apparently at a severe cache disadvantage
compared to EPYC Genoa.

Also, from the chipsandcheese piece: "As we noted in our previous article,
Prodigy has a higher compute to memory bandwidth ratio than current CPUs
and GPUs." This statement doesn't make any sense as a "bonus point" for
Tachyum considering the fact that EPYC Genoa will be well established
before the first Tachyum even sees first tape-out, let alone engineering
samples, let alone production chips.

And then: Anybody heard about AMD's MI300?