By: avianes (vianes.arthur.delete@this.protonmail.com), August 28, 2022 2:38 am
Room: Moderated Discussions
Anon (no.delete@this.spam.com) on August 27, 2022 9:54 pm wrote:
> Nobod (Nobod.delete@this.nospam.com) on August 27, 2022 9:21 am wrote:
> > Chips & Cheese analyzes Tachyum’s Revised Prodigy Architecture
> >
> > The new architecture is more traditional and more likely to work. Unfortunately it is trying to address
> > both HPC and datacenter server markets, but isn’t better than the alternatives at either job.
>
> Did anyone noticed the front end? Some days ago we were discussing about variable length instructions
> and too much fetch width, well, Tachyum thinks it is a good idea to have instruction 4 or
> 8 bytes wide, at 8 wide decode the instruction fetch is... 128 bytes, yep, 64 bytes would
> be enough in the worst case, but they think 128 bytes per cycle is better, I won't say that
> what Tachyum thinks matter at all, but I think this was one interesting point.
According to Chips and Cheese their cache-lines are 128B. So I guess the fetch just gets one 128B cache-line per cycle.
Also, cache-lines are 128B aligned while instructions are most likely 4B aligned (or not at all), so to fetch 64B of instruction from the L1i-cache regardless of alignment, a 128B aligned block seems appropriate.
I don't think there is any mystery here.
However, I would be curious about their instruction cache-coherence policy since the ISAs they intend to support do not have the same instruction cache-coherence policy.
> Nobod (Nobod.delete@this.nospam.com) on August 27, 2022 9:21 am wrote:
> > Chips & Cheese analyzes Tachyum’s Revised Prodigy Architecture
> >
> > The new architecture is more traditional and more likely to work. Unfortunately it is trying to address
> > both HPC and datacenter server markets, but isn’t better than the alternatives at either job.
>
> Did anyone noticed the front end? Some days ago we were discussing about variable length instructions
> and too much fetch width, well, Tachyum thinks it is a good idea to have instruction 4 or
> 8 bytes wide, at 8 wide decode the instruction fetch is... 128 bytes, yep, 64 bytes would
> be enough in the worst case, but they think 128 bytes per cycle is better, I won't say that
> what Tachyum thinks matter at all, but I think this was one interesting point.
According to Chips and Cheese their cache-lines are 128B. So I guess the fetch just gets one 128B cache-line per cycle.
Also, cache-lines are 128B aligned while instructions are most likely 4B aligned (or not at all), so to fetch 64B of instruction from the L1i-cache regardless of alignment, a 128B aligned block seems appropriate.
I don't think there is any mystery here.
However, I would be curious about their instruction cache-coherence policy since the ISAs they intend to support do not have the same instruction cache-coherence policy.
