By: --- (---.delete@this.redheron.com), August 28, 2022 2:24 pm
Room: Moderated Discussions
Anon (no.delete@this.spam.com) on August 27, 2022 9:54 pm wrote:
> Nobod (Nobod.delete@this.nospam.com) on August 27, 2022 9:21 am wrote:
> > Chips & Cheese analyzes Tachyum’s Revised Prodigy Architecture
> >
> > The new architecture is more traditional and more likely to work. Unfortunately it is trying to address
> > both HPC and datacenter server markets, but isn’t better than the alternatives at either job.
>
> Did anyone noticed the front end? Some days ago we were discussing about variable length instructions
> and too much fetch width, well, Tachyum thinks it is a good idea to have instruction 4 or
> 8 bytes wide, at 8 wide decode the instruction fetch is... 128 bytes, yep, 64 bytes would
> be enough in the worst case, but they think 128 bytes per cycle is better, I won't say that
> what Tachyum thinks matter at all, but I think this was one interesting point.
>
In and of itself that is not too startling. Apple's Fetch width is probably 16 instructions (at maximum), so 64B, and can straddle two cache lines.
Of course that's hooked up to what's meant to be a non-tiny, impressive core, not a weirdly unbalanced design.
It wouldn't be absolutely crazy if you're trying to save energy (I wouldn't roll my eyes if I learned that Apple's small core likewise can Fetch up to 16 instructions a cycle -- might as well get as much useful as you can in one gulp, then sleep Fetch for two or three cycles); but they don't look like they're trying to save every nanojoule the way Apple are.
> Nobod (Nobod.delete@this.nospam.com) on August 27, 2022 9:21 am wrote:
> > Chips & Cheese analyzes Tachyum’s Revised Prodigy Architecture
> >
> > The new architecture is more traditional and more likely to work. Unfortunately it is trying to address
> > both HPC and datacenter server markets, but isn’t better than the alternatives at either job.
>
> Did anyone noticed the front end? Some days ago we were discussing about variable length instructions
> and too much fetch width, well, Tachyum thinks it is a good idea to have instruction 4 or
> 8 bytes wide, at 8 wide decode the instruction fetch is... 128 bytes, yep, 64 bytes would
> be enough in the worst case, but they think 128 bytes per cycle is better, I won't say that
> what Tachyum thinks matter at all, but I think this was one interesting point.
>
In and of itself that is not too startling. Apple's Fetch width is probably 16 instructions (at maximum), so 64B, and can straddle two cache lines.
Of course that's hooked up to what's meant to be a non-tiny, impressive core, not a weirdly unbalanced design.
It wouldn't be absolutely crazy if you're trying to save energy (I wouldn't roll my eyes if I learned that Apple's small core likewise can Fetch up to 16 instructions a cycle -- might as well get as much useful as you can in one gulp, then sleep Fetch for two or three cycles); but they don't look like they're trying to save every nanojoule the way Apple are.
