By: --- (---.delete@this.redheron.com), August 29, 2022 9:53 am
Room: Moderated Discussions
anon2 (anon.delete@this.anon.com) on August 28, 2022 3:14 pm wrote:
> --- (---.delete@this.redheron.com) on August 28, 2022 2:24 pm wrote:
> > Anon (no.delete@this.spam.com) on August 27, 2022 9:54 pm wrote:
> > > Nobod (Nobod.delete@this.nospam.com) on August 27, 2022 9:21 am wrote:
> > > > Chips & Cheese analyzes Tachyum’s Revised Prodigy Architecture
> > > >
> > > > The new architecture is more traditional and more likely to work. Unfortunately it is trying to address
> > > > both HPC and datacenter server markets, but isn’t better than the alternatives at either job.
> > >
> > > Did anyone noticed the front end? Some days ago we were discussing about variable length instructions
> > > and too much fetch width, well, Tachyum thinks it is a good idea to have instruction 4 or
> > > 8 bytes wide, at 8 wide decode the instruction fetch is... 128 bytes, yep, 64 bytes would
> > > be enough in the worst case, but they think 128 bytes per cycle is better, I won't say that
> > > what Tachyum thinks matter at all, but I think this was one interesting point.
> > >
> >
> > In and of itself that is not too startling. Apple's Fetch width is probably
> > 16 instructions (at maximum), so 64B, and can straddle two cache lines.
>
> How probable would you say this is? What do you base it on?
What's the question?
I base the two line fetching on multiple patents. Apple have been fetching across cache lines since 2011 or so.
As for length, well think of the numbers. Apple can obviously sustain 8 instructions/cycle, so they can fetch wider than 8. They have a decoupled fetch architecture, of course, so they need to fetch *more* than 8 per cycle to help fill up the Instruction Queue (even as 8 per cycle are being extracted from the other end) in the face of short traces or occasional one or two cycle resteers.
A patent that's clearly referencing Swift (A6, 3-wide) has 8-wide Fetch, so 16-wide seems the obvious choice today. Possibly there was an intermediate phase of 12-wide for A7..A10.
> > Of course that's hooked up to what's meant to be a non-tiny,
> > impressive core, not a weirdly unbalanced design.
> >
> > It wouldn't be absolutely crazy if you're trying to save energy (I wouldn't roll my eyes if
> > I learned that Apple's small core likewise can Fetch up to 16 instructions a cycle -- might
> > as well get as much useful as you can in one gulp, then sleep Fetch for two or three cycles);
>
> That seems like the opposite of good energy efficiency to me. I doubt the small
> core would do that and also surprised about the big core if that is true of it.
>
> > but they don't look like they're trying to save every nanojoule the way Apple are.
>
>
> --- (---.delete@this.redheron.com) on August 28, 2022 2:24 pm wrote:
> > Anon (no.delete@this.spam.com) on August 27, 2022 9:54 pm wrote:
> > > Nobod (Nobod.delete@this.nospam.com) on August 27, 2022 9:21 am wrote:
> > > > Chips & Cheese analyzes Tachyum’s Revised Prodigy Architecture
> > > >
> > > > The new architecture is more traditional and more likely to work. Unfortunately it is trying to address
> > > > both HPC and datacenter server markets, but isn’t better than the alternatives at either job.
> > >
> > > Did anyone noticed the front end? Some days ago we were discussing about variable length instructions
> > > and too much fetch width, well, Tachyum thinks it is a good idea to have instruction 4 or
> > > 8 bytes wide, at 8 wide decode the instruction fetch is... 128 bytes, yep, 64 bytes would
> > > be enough in the worst case, but they think 128 bytes per cycle is better, I won't say that
> > > what Tachyum thinks matter at all, but I think this was one interesting point.
> > >
> >
> > In and of itself that is not too startling. Apple's Fetch width is probably
> > 16 instructions (at maximum), so 64B, and can straddle two cache lines.
>
> How probable would you say this is? What do you base it on?
What's the question?
I base the two line fetching on multiple patents. Apple have been fetching across cache lines since 2011 or so.
As for length, well think of the numbers. Apple can obviously sustain 8 instructions/cycle, so they can fetch wider than 8. They have a decoupled fetch architecture, of course, so they need to fetch *more* than 8 per cycle to help fill up the Instruction Queue (even as 8 per cycle are being extracted from the other end) in the face of short traces or occasional one or two cycle resteers.
A patent that's clearly referencing Swift (A6, 3-wide) has 8-wide Fetch, so 16-wide seems the obvious choice today. Possibly there was an intermediate phase of 12-wide for A7..A10.
> > Of course that's hooked up to what's meant to be a non-tiny,
> > impressive core, not a weirdly unbalanced design.
> >
> > It wouldn't be absolutely crazy if you're trying to save energy (I wouldn't roll my eyes if
> > I learned that Apple's small core likewise can Fetch up to 16 instructions a cycle -- might
> > as well get as much useful as you can in one gulp, then sleep Fetch for two or three cycles);
>
> That seems like the opposite of good energy efficiency to me. I doubt the small
> core would do that and also surprised about the big core if that is true of it.
>
> > but they don't look like they're trying to save every nanojoule the way Apple are.
>
>
