--- (---.delete@this.redheron.com) on August 29, 2022 9:53 am wrote:
> anon2 (anon.delete@this.anon.com) on August 28, 2022 3:14 pm wrote:
> > --- (---.delete@this.redheron.com) on August 28, 2022 2:24 pm wrote:
> > > Anon (no.delete@this.spam.com) on August 27, 2022 9:54 pm wrote:
> > > > Nobod (Nobod.delete@this.nospam.com) on August 27, 2022 9:21 am wrote:
> > > > > Chips & Cheese analyzes Tachyum’s Revised Prodigy Architecture
> > > > >
> > > > > The new architecture is more traditional and more likely to work. Unfortunately it is trying to address
> > > > > both HPC and datacenter server markets, but isn’t better than the alternatives at either job.
> > > >
> > > > Did anyone noticed the front end? Some days ago we were discussing about variable length instructions
> > > > and too much fetch width, well, Tachyum thinks it is a good idea to have instruction 4 or
> > > > 8 bytes wide, at 8 wide decode the instruction fetch is... 128 bytes, yep, 64 bytes would
> > > > be enough in the worst case, but they think 128 bytes per cycle is better, I won't say that
> > > > what Tachyum thinks matter at all, but I think this was one interesting point.
> > > >
> > >
> > > In and of itself that is not too startling. Apple's Fetch width is probably
> > > 16 instructions (at maximum), so 64B, and can straddle two cache lines.
> >
> > How probable would you say this is? What do you base it on?
>
> What's the question?

Exactly what you quoted.

> I base the two line fetching on multiple patents. Apple
> have been fetching across cache lines since 2011 or so.

That's very weak evidence. I thought you tested these things, it should be quite easy to observe (maybe unless there is some large or complex cache somewhere after I$).

> As for length, well think of the numbers. Apple can obviously sustain 8 instructions/cycle, so they
> can fetch wider than 8.

That does not follow.