By: Ivan (xxx.delete@this.xxx.xxx), August 30, 2022 12:00 am
Room: Moderated Discussions
Freddie (freddie.delete@this.witherden.org) on August 29, 2022 5:32 pm wrote:
> Saying that a lot of the value from AVX-512 comes from the ISA. Extra registers, embedded broadcasts
> in FMAs, and predication, to name a few. These are all useful. Moreover, most compilers will
> only emit 256-bit AVX-512 code by default unless explicitly told otherwise with -mprefer-vector-width=512
> due to historical down-clocking issues on Intel CPUs. Thus, assuming AMD have not messed up the
> implementation it is likely to have some utility even for non-ML code.
>
> Regards, Freddie.
Indeed. The RPCS3 emulator, for example, mostly benefits from the extra registers by its AVX-512 implementation. The extended vector width is an optional setting for small perf bonus.
> Saying that a lot of the value from AVX-512 comes from the ISA. Extra registers, embedded broadcasts
> in FMAs, and predication, to name a few. These are all useful. Moreover, most compilers will
> only emit 256-bit AVX-512 code by default unless explicitly told otherwise with -mprefer-vector-width=512
> due to historical down-clocking issues on Intel CPUs. Thus, assuming AMD have not messed up the
> implementation it is likely to have some utility even for non-ML code.
>
> Regards, Freddie.
Indeed. The RPCS3 emulator, for example, mostly benefits from the extra registers by its AVX-512 implementation. The extended vector width is an optional setting for small perf bonus.
