By: Heikki Kultala (heikki.kult.ala.delete@this.gmail.com), August 31, 2022 7:38 am
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on August 31, 2022 1:25 am wrote:
> anonymous2 (anonymous2.delete@this.example.com) on August 29, 2022 5:08 pm wrote:
> > AVX-512 (ISA details murky) on Zen 4 but 2 cycles vs 1 on Intel so only 256b internally.
> >
> > Small win for those who want the ISA, but from a performance perspective limited value?
> >
>
> In the list provided by AMD for contributors to enhanced performance at the same clock frequency,
> the second place after the new front-end was occupied by load/store enhancements.
.. and which has NOTHING to so with AVX-512.
AMD reported average 13% IPC improvement, and most of the software on the list used to calcualte the IPC improvemetn did not use AVX-512 at all.
> I interpret this AMD claim that in Zen 4 the load and store bandwidth between registers
> and the L1 data cache memory has been doubled in comparison with Zen 3.
That is not an interpretation. That is stupid speculation that has NOTHING to do with the original text where you claim to base it. IT's a VERY BAD misinterpretation.
> Most Intel CPUs that support AVX-512 can initiate in each clock cycle two 512-bit
> register-register operations, two 512-bit loads and one 512-bit store.
>
> Zen 3 can initiate in each cycle four 256-bit register-register operations, two 256-bit
> loads and one 256-bit store. By pairing 256-bit pipelines, Zen 4 would have been able
> to initiate in each cycle two 512-bit register-register operations and one 512-bit load,
> but one 512-bit store could have been initiated only every other cycle.
>
> That would have matched Intel in register-register operations, but would have been worse for load and store.
>
> So I assume that Zen 4 has been improved to be able to do two 512-bit loads and one 512-bit
> store per cycle.
This does not really makes sense at all.
Widening the memory data paths would be very expensive, and would do absolutely NOTHING to improve the performance of worklaods that do not use AVX-512. And almost all opf the software that AMD used to clculate this 13% IPC improvemetn does NOT use AVX-512.
The load/store improvement that gives part of that 13% has to be something totally unrelated to AVX-512.
Also, AFAIK there are no 512-bit registers on Zen4.
> Thus the throughput of Zen 4 for AVX-512 should match very closely that
> of the Intel CPUs which lack the second FMA unit, at the same clock frequency.
No. Makes no sense.
And then you post zillion lines of speculation that is based on totally false premises.
Forget it.
> anonymous2 (anonymous2.delete@this.example.com) on August 29, 2022 5:08 pm wrote:
> > AVX-512 (ISA details murky) on Zen 4 but 2 cycles vs 1 on Intel so only 256b internally.
> >
> > Small win for those who want the ISA, but from a performance perspective limited value?
> >
>
> In the list provided by AMD for contributors to enhanced performance at the same clock frequency,
> the second place after the new front-end was occupied by load/store enhancements.
.. and which has NOTHING to so with AVX-512.
AMD reported average 13% IPC improvement, and most of the software on the list used to calcualte the IPC improvemetn did not use AVX-512 at all.
> I interpret this AMD claim that in Zen 4 the load and store bandwidth between registers
> and the L1 data cache memory has been doubled in comparison with Zen 3.
That is not an interpretation. That is stupid speculation that has NOTHING to do with the original text where you claim to base it. IT's a VERY BAD misinterpretation.
> Most Intel CPUs that support AVX-512 can initiate in each clock cycle two 512-bit
> register-register operations, two 512-bit loads and one 512-bit store.
>
> Zen 3 can initiate in each cycle four 256-bit register-register operations, two 256-bit
> loads and one 256-bit store. By pairing 256-bit pipelines, Zen 4 would have been able
> to initiate in each cycle two 512-bit register-register operations and one 512-bit load,
> but one 512-bit store could have been initiated only every other cycle.
>
> That would have matched Intel in register-register operations, but would have been worse for load and store.
>
> So I assume that Zen 4 has been improved to be able to do two 512-bit loads and one 512-bit
> store per cycle.
This does not really makes sense at all.
Widening the memory data paths would be very expensive, and would do absolutely NOTHING to improve the performance of worklaods that do not use AVX-512. And almost all opf the software that AMD used to clculate this 13% IPC improvemetn does NOT use AVX-512.
The load/store improvement that gives part of that 13% has to be something totally unrelated to AVX-512.
Also, AFAIK there are no 512-bit registers on Zen4.
> Thus the throughput of Zen 4 for AVX-512 should match very closely that
> of the Intel CPUs which lack the second FMA unit, at the same clock frequency.
No. Makes no sense.
And then you post zillion lines of speculation that is based on totally false premises.
Forget it.