By: hobold (hobold.delete@this.vectorizer.org), September 16, 2022 1:03 pm
Room: Moderated Discussions
groo (charlie.delete@this.semiaccurate.com) on September 16, 2022 11:06 am wrote:
> It takes time to compute ECC data and L1s tend to be a bit tight on timings.
ECC computations might not have to be in the critical path. For example a load operation could forward its data without ECC check; sometime later you'd do the ECC computations; at the retire stage you would verify that the data and ECC codes match. On mismatch you'd have to replay from the erroneous load forward, possibly with a corrected error.
Obviously, bit errors would have to be really rare for this to make sense. If the goal is to get higher yield with more redundancy in the L1 cache, then ECC errors are expected to be a somewhat common occurrence, and this suggested scheme probably costs too much performance.
> It takes time to compute ECC data and L1s tend to be a bit tight on timings.
ECC computations might not have to be in the critical path. For example a load operation could forward its data without ECC check; sometime later you'd do the ECC computations; at the retire stage you would verify that the data and ECC codes match. On mismatch you'd have to replay from the erroneous load forward, possibly with a corrected error.
Obviously, bit errors would have to be really rare for this to make sense. If the goal is to get higher yield with more redundancy in the L1 cache, then ECC errors are expected to be a somewhat common occurrence, and this suggested scheme probably costs too much performance.