Data integrity of L1 caches

By: David Hess (davidwhess.delete@this.gmail.com), September 17, 2022 9:03 am
Room: Moderated Discussions
anon2 (anon.delete@this.anon.com) on September 15, 2022 7:04 pm wrote:
>
> A very long time ago I recall some CPUs had a bios selection between write-back and write-through
> L1, possibly integrity was the reason.

The Pentium 2 and 3 had that. I thought it was for some obscure compatibility reason.

> More recently Intel used a "DCU 16kB mode" option in
> its Xeons. This changed the data cache unit from 32kB 8-way associative, to mirrored 16kB 4-way
> halves and ECC achieved with parity finding correct copy. This seems to have gone away in favor
> of an allegedly more robust L1D sram cell and they have no ECC on writeback L1.

The way I understand it is that resistance to soft errors in the SRAM cell depends on the amount of stored charge, but higher stored charge requires greater power to perform a write operation because the drivers have to overcome the stored charge to perform the write. There are various ways to "unlock" the SRAM cell for the write, but they require more transistors and more space. In the case of CPU cache, access frequency is very high so the extra charge which would make the SRAM resistant to soft errors has a high cost in power.

> I have no issue with this. Reliability is limited by chance of more than correctable bitflips,
> if 1 bitflip has very small chance then reliability can be fine. I'm no array designer but it
> does seem like at some point at the very high end of reliability, having ECC would be better
> than increasing bit reliability. But perhaps for Xeon reliability goal that is enough.

I was thinking that the performance loss from having to do a read, modify, and write cycle was eventually high enough that the extra cost of implemented SRAM cache with the ability to have low power writes but retain high charge and low soft error rate became a worthwhile tradeoff.

I do not know how it would fit in here, but the high access frequency also contributes to increasing the soft error rate. The same memory accesses at a slower rate has fewer soft errors, so the L1 cache is particularly vulnerable.

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Data integrity of L1 cachesanon22022/09/15 06:04 PM
  Data integrity of L1 cachesGroo2022/09/15 10:46 PM
    Data integrity of L1 cachesanon22022/09/16 08:00 AM
      Data integrity of L1 cachesgroo2022/09/16 10:06 AM
        ECC outside critical path?hobold2022/09/16 12:03 PM
          ECC outside critical path?Mr. Camel2022/09/16 02:39 PM
            ECC outside critical path?anonymou52022/09/16 04:01 PM
          ECC outside critical path?anonymou52022/09/16 03:50 PM
            ECC outside critical path?hobold2022/09/17 05:57 AM
        Data integrity of L1 cachesanon22022/09/16 04:45 PM
  Data integrity of L1 cachesanon.12022/09/16 05:51 AM
    Data integrity of L1 cachesanon22022/09/16 08:04 AM
      Data integrity of L1 cachesBrett2022/09/16 11:12 AM
  Data integrity of L1 caches---2022/09/16 10:28 AM
    Data integrity of L1 cachesdmcq2022/09/16 12:41 PM
      Data integrity of L1 caches---2022/09/16 01:42 PM
    Data integrity of L1 cachesanon22022/09/16 04:49 PM
      Data integrity of L1 caches---2022/09/16 05:25 PM
        Read the thread (NT)anon22022/09/16 05:55 PM
        Data integrity of L1 cachesanon22022/09/16 05:57 PM
    Data integrity of L1 cachesMichael S2022/09/17 04:02 PM
  Data integrity of L1 cachesDavid Kanter2022/09/16 08:44 PM
    ECC word not necessarily full cache linePaul A. Clayton2022/09/17 09:59 AM
      ECC word not necessarily full cache lineDavid Kanter2022/09/18 11:29 AM
        ECC word not necessarily full cache lineAnon2022/09/18 11:54 AM
          ECC word not necessarily full cache linehobold2022/09/18 05:32 PM
            ECC word not necessarily full cache lineMichael S2022/09/19 07:47 AM
              ECC word not necessarily full cache linehobold2022/09/20 05:38 AM
                ECC word not necessarily full cache linedmcq2022/09/21 04:10 AM
                ECC word not necessarily full cache lineMichael S2022/09/21 05:55 AM
                  ECC word not necessarily full cache linehobold2022/09/21 12:59 PM
  Data integrity of L1 cachesDavid Hess2022/09/17 09:03 AM
  Data integrity of L1 cachesMichael S2022/09/17 04:12 PM
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