ECC word not necessarily full cache line

By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), September 17, 2022 9:59 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on September 16, 2022 9:44 pm wrote:
[snip]
> Most L1Ds are writeback. They also receive many partial writes (e.g., byte writes, 2B, 4B,
> etc.). ECC forces every write to trigger a full cache line read and write.

For L1 caches using ECC, the granularity is probably less than a cache line. The SRAM subarray word size is one reasonable ECC word size, but if 64-bit writes are common using a 64-bit ECC word might avoid enough reads to justify the area/power overhead. (Side thought: byte granular write enable is likely not to be supported with ECC-protected L1 caches, which might save a tiny bit of area and power.)

> In the L2, most
> writes are at full line granularity. In the L1, most writes are less than a full line.
>
> Also, ECC read+calc+write adds latency (as others noted above).

The latency does not seem that important. One would use a buffer anyway to provide recently written data, though greater latency would imply a larger buffer. Also a buffer alongside L1 could impact access latency of L1 contents.

Using L2 for the read for calculating ECC for sub-word writes effectively provides another set of access banks. L2 SRAM cells also tend to be more density optimized, so the cost of adding ECC bits would be reduced.

I suspect the tradeoffs are more complex than implied by my comments.
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TopicPosted ByDate
Data integrity of L1 cachesanon22022/09/15 06:04 PM
  Data integrity of L1 cachesGroo2022/09/15 10:46 PM
    Data integrity of L1 cachesanon22022/09/16 08:00 AM
      Data integrity of L1 cachesgroo2022/09/16 10:06 AM
        ECC outside critical path?hobold2022/09/16 12:03 PM
          ECC outside critical path?Mr. Camel2022/09/16 02:39 PM
            ECC outside critical path?anonymou52022/09/16 04:01 PM
          ECC outside critical path?anonymou52022/09/16 03:50 PM
            ECC outside critical path?hobold2022/09/17 05:57 AM
        Data integrity of L1 cachesanon22022/09/16 04:45 PM
  Data integrity of L1 cachesanon.12022/09/16 05:51 AM
    Data integrity of L1 cachesanon22022/09/16 08:04 AM
      Data integrity of L1 cachesBrett2022/09/16 11:12 AM
  Data integrity of L1 caches---2022/09/16 10:28 AM
    Data integrity of L1 cachesdmcq2022/09/16 12:41 PM
      Data integrity of L1 caches---2022/09/16 01:42 PM
    Data integrity of L1 cachesanon22022/09/16 04:49 PM
      Data integrity of L1 caches---2022/09/16 05:25 PM
        Read the thread (NT)anon22022/09/16 05:55 PM
        Data integrity of L1 cachesanon22022/09/16 05:57 PM
    Data integrity of L1 cachesMichael S2022/09/17 04:02 PM
  Data integrity of L1 cachesDavid Kanter2022/09/16 08:44 PM
    ECC word not necessarily full cache linePaul A. Clayton2022/09/17 09:59 AM
      ECC word not necessarily full cache lineDavid Kanter2022/09/18 11:29 AM
        ECC word not necessarily full cache lineAnon2022/09/18 11:54 AM
          ECC word not necessarily full cache linehobold2022/09/18 05:32 PM
            ECC word not necessarily full cache lineMichael S2022/09/19 07:47 AM
              ECC word not necessarily full cache linehobold2022/09/20 05:38 AM
                ECC word not necessarily full cache linedmcq2022/09/21 04:10 AM
                ECC word not necessarily full cache lineMichael S2022/09/21 05:55 AM
                  ECC word not necessarily full cache linehobold2022/09/21 12:59 PM
  Data integrity of L1 cachesDavid Hess2022/09/17 09:03 AM
  Data integrity of L1 cachesMichael S2022/09/17 04:12 PM
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