ECC word not necessarily full cache line

By: Michael S (already5chosen.delete@this.yahoo.com), September 19, 2022 7:47 am
Room: Moderated Discussions
hobold (hobold.delete@this.vectorizer.org) on September 18, 2022 6:32 pm wrote:
> Anon (no.delete@this.spam.com) on September 18, 2022 12:54 pm wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on September 18, 2022 12:29 pm wrote:
> > > That's true, but sub-line ECC has a much higher area overhead.
> > > So maybe I'd state it as 'power or area, take your pick'...
> >
> > Does it really matter? I mean, if you only modify 8 bytes out of the 64 bytes of the cache line then
> > old_value XOR new_value should give you enough information to update the ECC bits of the entire cache
> > line, only parity would actually appear per 8 bytes or so to not increase read latency too much.
>
> If I am not mistaken, there used to be specific ECC codes that have a geometric interpretation.
> With such a code, I think, oldVal XOR newVal would effectively yield a mirror plane (well,
> hyperplane ... something one dimension smaller than the entire code space). And then
> oldCode mirrored on that plane should result in the correct newCode.
>
> I don't remember the name of these specific codes, and if they are still in active use today. But my
> nebulous memory says it was this construction based on hypercubes such that any corner making up a valid
> code is surrounded by an edge subgraph of invalid codes, such that ... well, one can think of the neighbourhood
> as three rings. The innermost ring is all the single bit errors, so those are correctable. The 2nd ring
> is all two bit errors, so those are detectable. But the outermost 3rd ring is already made up of direct
> neighbours of other valid codes, so those will lead to an unrecoverable data loss.

What you described in your last sentence is normally referred as "hamming distance between legal codes >= 3" and is a necessary property of all SECDED codes.

As to real-world use, you probably would not find codes like that used for ECC of main memory in mid-high-end expensive server. More likely, code used there try to take advantage of non-uniform distribution nature of real-world errors (some memory chips are not as good as the others) in order to make correction more robust.

But for relatively small internal SRAM arrays expected distribution is pretty close to uniform, so such classic code should work fine. Without internal knowledge I fully expect that either classic Hamming codes or something very similar is used in practice for L2 cache ECC and also, on devices that have it, for L1D ECC.


< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Data integrity of L1 cachesanon22022/09/15 06:04 PM
  Data integrity of L1 cachesGroo2022/09/15 10:46 PM
    Data integrity of L1 cachesanon22022/09/16 08:00 AM
      Data integrity of L1 cachesgroo2022/09/16 10:06 AM
        ECC outside critical path?hobold2022/09/16 12:03 PM
          ECC outside critical path?Mr. Camel2022/09/16 02:39 PM
            ECC outside critical path?anonymou52022/09/16 04:01 PM
          ECC outside critical path?anonymou52022/09/16 03:50 PM
            ECC outside critical path?hobold2022/09/17 05:57 AM
        Data integrity of L1 cachesanon22022/09/16 04:45 PM
  Data integrity of L1 cachesanon.12022/09/16 05:51 AM
    Data integrity of L1 cachesanon22022/09/16 08:04 AM
      Data integrity of L1 cachesBrett2022/09/16 11:12 AM
  Data integrity of L1 caches---2022/09/16 10:28 AM
    Data integrity of L1 cachesdmcq2022/09/16 12:41 PM
      Data integrity of L1 caches---2022/09/16 01:42 PM
    Data integrity of L1 cachesanon22022/09/16 04:49 PM
      Data integrity of L1 caches---2022/09/16 05:25 PM
        Read the thread (NT)anon22022/09/16 05:55 PM
        Data integrity of L1 cachesanon22022/09/16 05:57 PM
    Data integrity of L1 cachesMichael S2022/09/17 04:02 PM
  Data integrity of L1 cachesDavid Kanter2022/09/16 08:44 PM
    ECC word not necessarily full cache linePaul A. Clayton2022/09/17 09:59 AM
      ECC word not necessarily full cache lineDavid Kanter2022/09/18 11:29 AM
        ECC word not necessarily full cache lineAnon2022/09/18 11:54 AM
          ECC word not necessarily full cache linehobold2022/09/18 05:32 PM
            ECC word not necessarily full cache lineMichael S2022/09/19 07:47 AM
              ECC word not necessarily full cache linehobold2022/09/20 05:38 AM
                ECC word not necessarily full cache linedmcq2022/09/21 04:10 AM
                ECC word not necessarily full cache lineMichael S2022/09/21 05:55 AM
                  ECC word not necessarily full cache linehobold2022/09/21 12:59 PM
  Data integrity of L1 cachesDavid Hess2022/09/17 09:03 AM
  Data integrity of L1 cachesMichael S2022/09/17 04:12 PM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell tangerine? ūüćä