ECC word not necessarily full cache line

By: Michael S (already5chosen.delete@this.yahoo.com), September 21, 2022 5:55 am
Room: Moderated Discussions
hobold (hobold.delete@this.vectorizer.org) on September 20, 2022 6:38 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on September 19, 2022 8:47 am wrote:
> [...]
> > Without internal knowledge I fully expect that either classic Hamming codes or something
> > very similar is used in practice for L2 cache ECC and also, on devices that have it, for L1D ECC.
>
> Hamming distances sounds about right. What I was trying to add to the discussion
> is analogous to homomorphic encryption: the possibility to do correct computation
> on encoded data without decoding it first and re-encoding it afterwards.
>
> In the case of encryption this is usually inefficient (because the payload data has to remain verifiably secret
> the whole time). But for ECC purposes there might be codes that allow for efficient partial updates.


That is possible and relatively easy for any linear systematic code.
And I am pretty sure that codes, used for L1/L2 cache ECC are linear systematic codes.
So, no problems here.
However your idea does not work for other, more important, reason: it weakens a protection.
For proper protection *every* read from SRAM should be followed by correction of possible single-bit error. You can not do it when you read partial block instead of the full block.
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Data integrity of L1 cachesanon22022/09/15 06:04 PM
  Data integrity of L1 cachesGroo2022/09/15 10:46 PM
    Data integrity of L1 cachesanon22022/09/16 08:00 AM
      Data integrity of L1 cachesgroo2022/09/16 10:06 AM
        ECC outside critical path?hobold2022/09/16 12:03 PM
          ECC outside critical path?Mr. Camel2022/09/16 02:39 PM
            ECC outside critical path?anonymou52022/09/16 04:01 PM
          ECC outside critical path?anonymou52022/09/16 03:50 PM
            ECC outside critical path?hobold2022/09/17 05:57 AM
        Data integrity of L1 cachesanon22022/09/16 04:45 PM
  Data integrity of L1 cachesanon.12022/09/16 05:51 AM
    Data integrity of L1 cachesanon22022/09/16 08:04 AM
      Data integrity of L1 cachesBrett2022/09/16 11:12 AM
  Data integrity of L1 caches---2022/09/16 10:28 AM
    Data integrity of L1 cachesdmcq2022/09/16 12:41 PM
      Data integrity of L1 caches---2022/09/16 01:42 PM
    Data integrity of L1 cachesanon22022/09/16 04:49 PM
      Data integrity of L1 caches---2022/09/16 05:25 PM
        Read the thread (NT)anon22022/09/16 05:55 PM
        Data integrity of L1 cachesanon22022/09/16 05:57 PM
    Data integrity of L1 cachesMichael S2022/09/17 04:02 PM
  Data integrity of L1 cachesDavid Kanter2022/09/16 08:44 PM
    ECC word not necessarily full cache linePaul A. Clayton2022/09/17 09:59 AM
      ECC word not necessarily full cache lineDavid Kanter2022/09/18 11:29 AM
        ECC word not necessarily full cache lineAnon2022/09/18 11:54 AM
          ECC word not necessarily full cache linehobold2022/09/18 05:32 PM
            ECC word not necessarily full cache lineMichael S2022/09/19 07:47 AM
              ECC word not necessarily full cache linehobold2022/09/20 05:38 AM
                ECC word not necessarily full cache linedmcq2022/09/21 04:10 AM
                ECC word not necessarily full cache lineMichael S2022/09/21 05:55 AM
                  ECC word not necessarily full cache linehobold2022/09/21 12:59 PM
  Data integrity of L1 cachesDavid Hess2022/09/17 09:03 AM
  Data integrity of L1 cachesMichael S2022/09/17 04:12 PM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell tangerine? ūüćä