By: Michael S (already5chosen.delete@this.yahoo.com), September 21, 2022 6:55 am
Room: Moderated Discussions
hobold (hobold.delete@this.vectorizer.org) on September 20, 2022 6:38 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on September 19, 2022 8:47 am wrote:
> [...]
> > Without internal knowledge I fully expect that either classic Hamming codes or something
> > very similar is used in practice for L2 cache ECC and also, on devices that have it, for L1D ECC.
>
> Hamming distances sounds about right. What I was trying to add to the discussion
> is analogous to homomorphic encryption: the possibility to do correct computation
> on encoded data without decoding it first and re-encoding it afterwards.
>
> In the case of encryption this is usually inefficient (because the payload data has to remain verifiably secret
> the whole time). But for ECC purposes there might be codes that allow for efficient partial updates.
That is possible and relatively easy for any linear systematic code.
And I am pretty sure that codes, used for L1/L2 cache ECC are linear systematic codes.
So, no problems here.
However your idea does not work for other, more important, reason: it weakens a protection.
For proper protection *every* read from SRAM should be followed by correction of possible single-bit error. You can not do it when you read partial block instead of the full block.
> Michael S (already5chosen.delete@this.yahoo.com) on September 19, 2022 8:47 am wrote:
> [...]
> > Without internal knowledge I fully expect that either classic Hamming codes or something
> > very similar is used in practice for L2 cache ECC and also, on devices that have it, for L1D ECC.
>
> Hamming distances sounds about right. What I was trying to add to the discussion
> is analogous to homomorphic encryption: the possibility to do correct computation
> on encoded data without decoding it first and re-encoding it afterwards.
>
> In the case of encryption this is usually inefficient (because the payload data has to remain verifiably secret
> the whole time). But for ECC purposes there might be codes that allow for efficient partial updates.
That is possible and relatively easy for any linear systematic code.
And I am pretty sure that codes, used for L1/L2 cache ECC are linear systematic codes.
So, no problems here.
However your idea does not work for other, more important, reason: it weakens a protection.
For proper protection *every* read from SRAM should be followed by correction of possible single-bit error. You can not do it when you read partial block instead of the full block.