noko (noko.delete@this.noko.com) on September 29, 2022 8:02 pm wrote:
> https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
>
> I guess actual details won't be released until sometime next year. But some interesting points:
>
> - SME2 just a year after SME
> - Multi-vector instructions, I'm guessing this basically RVV's vector groups?
> - ARM's 3rd try to kill ROP, this time with a shadow stack
> - A "Hybrid Vector Length Agnostic" programming model for SVE2, any clue what that means?



I have no idea about what "multi-vector operations" means, but e.g. doing a matrix-vector multiplication simultaneously with multiple vectors, in a single operation, might improve the throughput in comparison with doing separate matrix-vector multiplications.


On the other hand, "range prefetches" sounds more clearly like a very desirable addition, if they would allow the control of the destination of the prefetch, e.g. to registers or to L1 cache or to L2 cache and/or if they would also do the gathering of matrix rows/columns into a compact range. On CPUs with cache memories, and especially with multiple levels of cache memories, it is always desirable to have a more predictable and robust means to ensure that matrix blocks are located in the right level of cache memory at the right time.