noko (noko.delete@this.noko.com) on September 29, 2022 8:02 pm wrote:
> https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
>
> I guess actual details won't be released until sometime next year. But some interesting points:
>
> - SME2 just a year after SME
> - Multi-vector instructions, I'm guessing this basically RVV's vector groups?
> - ARM's 3rd try to kill ROP, this time with a shadow stack
> - A "Hybrid Vector Length Agnostic" programming model for SVE2, any clue what that means?

Thanks for that. The virttual memory additions are interesting too. The permissions overlay for page table entries - very like on their microcontrollers and can be very convenient for JIT's like they say. Plus a hardenng of page tables against attacks. And who on earth was asking for 128 bit page descriptors? I this something about preparing for their Morello or are people really already asking for more than 2^64 physical memory perhaps in an array processor? Or is X-Point going to work at long last now Intel has cancelled it? ;-)

I would guess multi-vector instructions mneans having a predicate associated with each point of the SME array and doing an operations other than just FMA with all those vectors and another operand vector. Anyway hope we see soon what they're up to.

Hybrid vector length agnostic? God knows!