By: Anon (no.delete@this.spam.com), November 5, 2022 4:10 am
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on November 5, 2022 3:50 am wrote:
> Exactly like they have done it in their previous Zen 3 scheduler, where some operations can be done in any
> of the four 256-bit pipelines, while some operations could be done in anyone of only two of the pipelines.
>
> If the four pipelines are coupled into two pipeline pairs for scheduling 512-bit operations,
> the scheduling is similar to the scheduling of the 256-bit operations, but simpler.
>
> It can be done by the same circuits, e.g. by forcing the inputs that show the busy state of the 2nd
> pipeline in a pair to the busy value, because scheduling the 512-bit operations (when the splitting
> is done after scheduling) is like always choosing the 1st pipeline in a pair of 256-bit pipelines.
My understanding o Zen FPU is that there are two schedullers, each with FADD, FMAD and FSTORE units, if you scheduller 512 bits operations to the 1st scheduller and just mark the second one as busy then you would only have half the schedullers entries available, like if the split was before the scheduller, if someone claims the split happens after the scheduller than it implies 512 bit instructions are being sent to both schedullers so all entries are available, and it is not so simple to tell the other scheduller the unit is busy.
In contrast to Intel design which uses an unified scheduller and marking one port as busy for a long time solves the problem, and would have the behaviour identified by cheese and chips testing.
> Exactly like they have done it in their previous Zen 3 scheduler, where some operations can be done in any
> of the four 256-bit pipelines, while some operations could be done in anyone of only two of the pipelines.
>
> If the four pipelines are coupled into two pipeline pairs for scheduling 512-bit operations,
> the scheduling is similar to the scheduling of the 256-bit operations, but simpler.
>
> It can be done by the same circuits, e.g. by forcing the inputs that show the busy state of the 2nd
> pipeline in a pair to the busy value, because scheduling the 512-bit operations (when the splitting
> is done after scheduling) is like always choosing the 1st pipeline in a pair of 256-bit pipelines.
My understanding o Zen FPU is that there are two schedullers, each with FADD, FMAD and FSTORE units, if you scheduller 512 bits operations to the 1st scheduller and just mark the second one as busy then you would only have half the schedullers entries available, like if the split was before the scheduller, if someone claims the split happens after the scheduller than it implies 512 bit instructions are being sent to both schedullers so all entries are available, and it is not so simple to tell the other scheduller the unit is busy.
In contrast to Intel design which uses an unified scheduller and marking one port as busy for a long time solves the problem, and would have the behaviour identified by cheese and chips testing.