Just wanted to point everyone to Dougall's recent fascinating post on Rosetta 2 performance. I learned something I didn't know before - that Apple implements a custom extension which generates two extra flag bits on certain ALU instructions.

https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-fast/

Dougall, a very minor thing you might want to add - While TSO isn't unique to Apple's Arm cores and is legal ordering for an Arm implementation, there's still something custom here: dynamically reconfigurable memory ordering. When the Darwin scheduler gives a timeslice to a Rosetta 2 process, it configures that core for TSO, and when the timeslice ends, the scheduler returns the core to more relaxed ordering.

I don't have a link but I remember reading about people disabling SIP, hacking the Darwin kernel to run arm64 processes in TSO mode, and discovering that it had a performance penalty. Which is presumably why they bothered with a custom mode bit.