By: Captain Obvious (obvious.delete@this.here.net), November 21, 2022 11:29 am
Room: Moderated Discussions
Foyle (nope.delete@this.nope.com) on November 21, 2022 7:58 am wrote:
> Andrey (andrey.semashev.delete@this.gmail.com) on November 21, 2022 4:23 am wrote:
> > This will probably be a naive and silly question, but I'm curious.
> >
> > Assuming that a logical one is represented with a higher voltage than a logical zero in the IC,
> > is it fair to say that ones are more expensive to process in terms of power and heat? That is,
> > if it takes more energy to charge a DRAM or SRAM cell to a level of one (in case of DRAM - also
> > to refresh it), if it takes more voltage to transfer the signal along the traces, if this voltage
> > makes more heat in the transistors implementing a logical circuit within the IC, thus causing
> > more leakage current, wouldn't it be more expensive? I wonder if someone tested this.
> >
> > If there is a measurable difference, wouldn't it make sense to account for that when designing the ICs and
> > writing software? On the hardware level, it might make sense
> > to process negated signals or a mixture of positive
> > and negated signals to reduce the number of "ones" or at least make them statistically closer to "zeros" so
> > to reduce the possible power consumption spikes. In software,
> > it would make sense to prefer zero or power-of-two
> > representations of data more often. Of course, it is not
> > possible to have a useful machine (both in hardware
> > and software) processing only zeros, but some difference could be made. Or could it?
> >
>
> I don't know about computation, but this has long been recognized and designed for in data transmission. For
> example memory buses since GDDR4 use DBI (data bus inversion) to minimize the number of energy-expensive
> line states, and apparently some buses use inversion encoding to minimize the number of transitions.
Interesting. So while it might be pointless on SRAM (discussed to death above), DRAM does have a difference between states, and the DRAM chips already "know" which state has less ones (or zeros), so can choose between them. I'd assume that writing a one requires more energy (charging the capacitor) and this has to be done for each DRAM page on every (non-page hit) read, write, and refresh.
Of course, if this is done it is done internally in hardware and invisible to software. Would anyone publish it if they did this?
> Andrey (andrey.semashev.delete@this.gmail.com) on November 21, 2022 4:23 am wrote:
> > This will probably be a naive and silly question, but I'm curious.
> >
> > Assuming that a logical one is represented with a higher voltage than a logical zero in the IC,
> > is it fair to say that ones are more expensive to process in terms of power and heat? That is,
> > if it takes more energy to charge a DRAM or SRAM cell to a level of one (in case of DRAM - also
> > to refresh it), if it takes more voltage to transfer the signal along the traces, if this voltage
> > makes more heat in the transistors implementing a logical circuit within the IC, thus causing
> > more leakage current, wouldn't it be more expensive? I wonder if someone tested this.
> >
> > If there is a measurable difference, wouldn't it make sense to account for that when designing the ICs and
> > writing software? On the hardware level, it might make sense
> > to process negated signals or a mixture of positive
> > and negated signals to reduce the number of "ones" or at least make them statistically closer to "zeros" so
> > to reduce the possible power consumption spikes. In software,
> > it would make sense to prefer zero or power-of-two
> > representations of data more often. Of course, it is not
> > possible to have a useful machine (both in hardware
> > and software) processing only zeros, but some difference could be made. Or could it?
> >
>
> I don't know about computation, but this has long been recognized and designed for in data transmission. For
> example memory buses since GDDR4 use DBI (data bus inversion) to minimize the number of energy-expensive
> line states, and apparently some buses use inversion encoding to minimize the number of transitions.
Interesting. So while it might be pointless on SRAM (discussed to death above), DRAM does have a difference between states, and the DRAM chips already "know" which state has less ones (or zeros), so can choose between them. I'd assume that writing a one requires more energy (charging the capacitor) and this has to be done for each DRAM page on every (non-page hit) read, write, and refresh.
Of course, if this is done it is done internally in hardware and invisible to software. Would anyone publish it if they did this?
| Topic | Posted By | Date |
|---|---|---|
| Is 1 more expensive than 0? | Andrey | 2022/11/21 05:23 AM |
| Is 1 more expensive than 0? | Juha Lainema | 2022/11/21 06:15 AM |
| Is 1 more expensive than 0? | Adrian | 2022/11/21 07:21 AM |
| Is 1 more expensive than 0? | anon2 | 2022/11/21 05:29 PM |
| switching between 0 and 1 is what consumes power | Heikki Kultala | 2022/11/21 07:23 AM |
| Thank you all for your answers. (NT) | Andrey | 2022/11/21 08:29 AM |
| Is 1 more expensive than 0? | Foyle | 2022/11/21 08:58 AM |
| Is 1 more expensive than 0? | Michael S | 2022/11/21 10:51 AM |
| Is 1 more expensive than 0? | Captain Obvious | 2022/11/21 11:29 AM |
| obvious stuff | anonymou5 | 2022/11/21 02:25 PM |
| obvious stuff | Andrey | 2022/11/21 02:50 PM |
| obvious stuff | Michael S | 2022/11/21 03:43 PM |
| SRAM is bistable | Anon | 2022/11/21 10:50 AM |
| SRAM is bistable | Andrew Clough | 2022/11/22 05:53 AM |
| NAND Flash 1 and 0 | jokerman | 2022/11/24 01:13 PM |
| NAND Flash 1 and 0 | Joern Engel | 2022/11/25 12:00 AM |
| NAND Flash 1 and 0 | Ungo | 2022/11/25 02:26 AM |
| The ECC needs to be stored. as ones ane zeroes (NT) | Heikki Kultala | 2022/11/25 08:31 AM |
| The ECC needs to be stored. as ones ane zeroes | anon2 | 2022/11/25 05:07 PM |
| The ECC needs to be stored. as ones ane zeroes | Heikki Kultala | 2022/11/26 12:48 AM |
| The ECC needs to be stored. as ones ane zeroes | anon2 | 2022/11/26 02:00 AM |
