Adrian (a.delete@this.acm.org) on November 21, 2022 6:21 am wrote:
> Andrey (andrey.semashev.delete@this.gmail.com) on November 21, 2022 4:23 am wrote:
> > This will probably be a naive and silly question, but I'm curious.
> >
> > Assuming that a logical one is represented with a higher voltage than a logical zero in the IC,
> > is it fair to say that ones are more expensive to process in terms of power and heat? That is,
> > if it takes more energy to charge a DRAM or SRAM cell to a level of one (in case of DRAM - also
> > to refresh it), if it takes more voltage to transfer the signal along the traces, if this voltage
> > makes more heat in the transistors implementing a logical circuit within the IC, thus causing
> > more leakage current, wouldn't it be more expensive? I wonder if someone tested this.
> >
> > If there is a measurable difference, wouldn't it make sense to account for that when designing the ICs and
> > writing software? On the hardware level, it might make sense
> > to process negated signals or a mixture of positive
> > and negated signals to reduce the number of "ones" or at least make them statistically closer to "zeros" so
> > to reduce the possible power consumption spikes. In software,
> > it would make sense to prefer zero or power-of-two
> > representations of data more often. Of course, it is not
> > possible to have a useful machine (both in hardware
> > and software) processing only zeros, but some difference could be made. Or could it?
> >
>
>
> As someone else has already said, in the case of static CMOS logic, which is the most
> frequently used kind of logic in modern ICs, except for the energy wasted by leakage
> currents, which also has weak correlation, if any, with the bit patterns, the energy
> consumption is determined by the number of bit transitions, not by their values.
>
> There are a few cases when the computation of some complex functions can be decomposed in several
> different ways as a cascade of simpler stages, and in some of the ways there are fewer bit transitions
> in the intermediate stages than in other ways, during a function computation.
>
> In such cases, it may make sense to choose the decomposition with fewer bit transitions
> per computation, because that will lower the power consumption, despite the fact that
> other decompositions may need fewer logical gates, i.e. less chip area.
>
> In the case of DRAM, normally one of the bit states is stable, as it corresponds to
> the state at thermal equilibrium, while the other state is unstable due to leakage
> current and it will decay into the stable state, unless refreshes often enough.
>
> Whether the stable state is "1" or "0" can vary between DRAM models. Therefore, if there would be
> a large amount of data that would be stored in a DRAM for a long time without changes, choosing to
> store it either directly or in negated form, depending on which variant would have fewer bits in
> the unstable state, might save some of the energy spent for memory refreshing. Nevertheless, it is
> likely that the energy saved in this way is too small to make the complications worthwhile.

Vaguely related, NAND storage uses whitening functions to encode data to give more even balance and distribution of 0 and 1 bits, I believe this is done for retention although I don't recall the mechanism involved, It could possibly have been for wear leveling. I wonder if DRAMs have any use for such a thing.