By: Andrew Clough (someone.delete@this.somewhere.com), November 22, 2022 5:53 am
Room: Moderated Discussions
Anon (no.delete@this.spam.com) on November 21, 2022 9:50 am wrote:
> Andrey (andrey.semashev.delete@this.gmail.com) on November 21, 2022 4:23 am wrote:
> > Assuming that a logical one is represented with a higher voltage than a logical zero in the IC,
> > is it fair to say that ones are more expensive to process in terms of power and heat? That is,
> > if it takes more energy to charge a DRAM or SRAM cell to a level of one (in case of DRAM - also
> > to refresh it), if it takes more voltage to transfer the signal along the traces, if this voltage
> > makes more heat in the transistors implementing a logical circuit within the IC, thus causing
> > more leakage current, wouldn't it be more expensive? I wonder if someone tested this.
>
> You already got many good answears, I just want to point out that SRAM is bistable, that means one side have
> the complementary charge of the other, so no reason for one of the values to leak less power then the other.
I seem to recall that many years ago, when I was last in the weeds on these issues, minimum width NFETs leaked more than PFETs so there was actually a bit of asymmetry. No idea if that still applies in the modern era of 3D structures, strained silicon, etc.
> Andrey (andrey.semashev.delete@this.gmail.com) on November 21, 2022 4:23 am wrote:
> > Assuming that a logical one is represented with a higher voltage than a logical zero in the IC,
> > is it fair to say that ones are more expensive to process in terms of power and heat? That is,
> > if it takes more energy to charge a DRAM or SRAM cell to a level of one (in case of DRAM - also
> > to refresh it), if it takes more voltage to transfer the signal along the traces, if this voltage
> > makes more heat in the transistors implementing a logical circuit within the IC, thus causing
> > more leakage current, wouldn't it be more expensive? I wonder if someone tested this.
>
> You already got many good answears, I just want to point out that SRAM is bistable, that means one side have
> the complementary charge of the other, so no reason for one of the values to leak less power then the other.
I seem to recall that many years ago, when I was last in the weeds on these issues, minimum width NFETs leaked more than PFETs so there was actually a bit of asymmetry. No idea if that still applies in the modern era of 3D structures, strained silicon, etc.
| Topic | Posted By | Date |
|---|---|---|
| Is 1 more expensive than 0? | Andrey | 2022/11/21 05:23 AM |
| Is 1 more expensive than 0? | Juha Lainema | 2022/11/21 06:15 AM |
| Is 1 more expensive than 0? | Adrian | 2022/11/21 07:21 AM |
| Is 1 more expensive than 0? | anon2 | 2022/11/21 05:29 PM |
| switching between 0 and 1 is what consumes power | Heikki Kultala | 2022/11/21 07:23 AM |
| Thank you all for your answers. (NT) | Andrey | 2022/11/21 08:29 AM |
| Is 1 more expensive than 0? | Foyle | 2022/11/21 08:58 AM |
| Is 1 more expensive than 0? | Michael S | 2022/11/21 10:51 AM |
| Is 1 more expensive than 0? | Captain Obvious | 2022/11/21 11:29 AM |
| obvious stuff | anonymou5 | 2022/11/21 02:25 PM |
| obvious stuff | Andrey | 2022/11/21 02:50 PM |
| obvious stuff | Michael S | 2022/11/21 03:43 PM |
| SRAM is bistable | Anon | 2022/11/21 10:50 AM |
| SRAM is bistable | Andrew Clough | 2022/11/22 05:53 AM |
| NAND Flash 1 and 0 | jokerman | 2022/11/24 01:13 PM |
| NAND Flash 1 and 0 | Joern Engel | 2022/11/25 12:00 AM |
| NAND Flash 1 and 0 | Ungo | 2022/11/25 02:26 AM |
| The ECC needs to be stored. as ones ane zeroes (NT) | Heikki Kultala | 2022/11/25 08:31 AM |
| The ECC needs to be stored. as ones ane zeroes | anon2 | 2022/11/25 05:07 PM |
| The ECC needs to be stored. as ones ane zeroes | Heikki Kultala | 2022/11/26 12:48 AM |
| The ECC needs to be stored. as ones ane zeroes | anon2 | 2022/11/26 02:00 AM |
