What happens when DRAM has more bandwidth than Layer 3 cache?

By: Simon Farnsworth (simon.delete@this.farnz.org.uk), December 8, 2022 7:22 am
Room: Moderated Discussions
Etienne (etienne_lorrain.delete@this.yahoo.fr) on December 8, 2022 6:20 am wrote:
> Looks like my AMD Ryzen 9 7950x has a L3 cache bandwidth of 63.9 GB/s, my current DRAM DDR5
> has either 49.6 GB/s (Jedec) or 52.5 GB/s (AMD Expo) measured by memtest86 UEFI.
> It seems some companies are increasing DRAM bandwidth: 8Gbps DDR5.
>
> I assume latency to L3 cache is still probably better than latency to
> DRAM, but in simple terms, do we still need L3 cache in processors?

A critical difference between peak DRAM throughput, and L3 throughput, is that L3 throughput is independent of access pattern (as long as you never leave L3, of course) - you get the same throughput from L3 whether you read cachelines sequentially, or whether you read cachelines in a random order, and you get the same throughput when writing whether you write sequentially, or whether you write in a random order. There's also no penalty for mixing writes and reads - the timings are the same for read then read another line, as for read then write and for write then read and for write then write another line.

DDR5 doesn't offer that - your throughput is lower if you read or write 64 byte chunks at random throughput the chip than if you arrange to stay in the same bank group as much as possible. There's also a small penalty for mixing reads and writes, so you benefit from L3 if it lets you do more writes in sequence before switching back to reads or vice-versa.
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TopicPosted ByDate
What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 06:20 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Simon Farnsworth2022/12/08 07:22 AM
    bandwidth*delay productMichael S2022/12/08 08:06 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 10:44 AM
      What happens when DRAM has more bandwidth than Layer 3 cache?blaine2022/12/08 05:07 PM
  What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 07:32 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 08:05 AM
      What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 08:13 AM
        What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 01:56 PM
  What happens when DRAM has more bandwidth than Layer 3 cache?Peter E. fry2022/12/08 08:20 AM
  Programs do not see bandwidth. Programs only see latency. Heikki Kultala2022/12/08 08:26 AM
    Programs do not see bandwidth. Programs only see latency. Chester2022/12/08 11:07 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Doug S2022/12/08 09:31 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 10:32 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 02:42 PM
      What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 03:54 PM
        What happens when DRAM has more bandwidth than Layer 3 cache?Anon2022/12/20 06:46 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Andrey2022/12/08 03:10 PM
    What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/14 03:20 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Gionatan Danti2022/12/09 12:31 AM
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