By: Doug S (foo.delete@this.bar.bar), December 8, 2022 9:31 am
Room: Moderated Discussions
Etienne (etienne_lorrain.delete@this.yahoo.fr) on December 8, 2022 6:20 am wrote:
> Looks like my AMD Ryzen 9 7950x has a L3 cache bandwidth of 63.9 GB/s, my current DRAM DDR5
> has either 49.6 GB/s (Jedec) or 52.5 GB/s (AMD Expo) measured by memtest86 UEFI.
> It seems some companies are increasing DRAM bandwidth: 8Gbps DDR5.
>
> I assume latency to L3 cache is still probably better than latency to
> DRAM, but in simple terms, do we still need L3 cache in processors?
Cache was invented primarily to reduce latency, not increase bandwidth. Which would you rather have available to you, trains that to go your destination every 15 minutes holding 100 people, or trains that go there once an hour holding 400 people? The bandwidth is the same, so the latter is just as good, right?
That's ignoring the facts others have explained about how DRAM works where 400 people only fit on the train in ideal (and generally unrealistic) situations, but most of the time the carrying capacity is far lower.
> Looks like my AMD Ryzen 9 7950x has a L3 cache bandwidth of 63.9 GB/s, my current DRAM DDR5
> has either 49.6 GB/s (Jedec) or 52.5 GB/s (AMD Expo) measured by memtest86 UEFI.
> It seems some companies are increasing DRAM bandwidth: 8Gbps DDR5.
>
> I assume latency to L3 cache is still probably better than latency to
> DRAM, but in simple terms, do we still need L3 cache in processors?
Cache was invented primarily to reduce latency, not increase bandwidth. Which would you rather have available to you, trains that to go your destination every 15 minutes holding 100 people, or trains that go there once an hour holding 400 people? The bandwidth is the same, so the latter is just as good, right?
That's ignoring the facts others have explained about how DRAM works where 400 people only fit on the train in ideal (and generally unrealistic) situations, but most of the time the carrying capacity is far lower.
