What happens when DRAM has more bandwidth than Layer 3 cache?

By: Michael S (already5chosen.delete@this.yahoo.com), December 8, 2022 2:42 pm
Room: Moderated Discussions
--- (---.delete@this.redheron.com) on December 8, 2022 10:32 am wrote:
> Etienne (etienne_lorrain.delete@this.yahoo.fr) on December 8, 2022 6:20 am wrote:
>
> Look at what Apple does.
> (a) Apple does not have L3. Instead we get something like the capacity of L3 with
> the latency of L2 in the very large L2 caches. This is feasible if you cluster
> cores to share an L2, something that makes sense for other reasons as well.
> Various ARM designs have done this and this is what Intel E-cores do, isn't it?
>

It isn't.
In Alder Lake and Raptor Lake E-core modules are sharing L3 cache with P-cores.

ARM:
AWS Graviton2 has decent L3 cache, but Graviton3's is twice bigger.
Ampere Altra Max has rather small SLC. Probably too small to be considered L3 cache.
As to high end Qualcomm/Microsoft, I would like to know myself. So far I was not able to find any info.
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TopicPosted ByDate
What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 06:20 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Simon Farnsworth2022/12/08 07:22 AM
    bandwidth*delay productMichael S2022/12/08 08:06 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 10:44 AM
      What happens when DRAM has more bandwidth than Layer 3 cache?blaine2022/12/08 05:07 PM
  What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 07:32 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 08:05 AM
      What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 08:13 AM
        What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 01:56 PM
  What happens when DRAM has more bandwidth than Layer 3 cache?Peter E. fry2022/12/08 08:20 AM
  Programs do not see bandwidth. Programs only see latency. Heikki Kultala2022/12/08 08:26 AM
    Programs do not see bandwidth. Programs only see latency. Chester2022/12/08 11:07 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Doug S2022/12/08 09:31 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 10:32 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 02:42 PM
      What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 03:54 PM
        What happens when DRAM has more bandwidth than Layer 3 cache?Anon2022/12/20 06:46 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Andrey2022/12/08 03:10 PM
    What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/14 03:20 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Gionatan Danti2022/12/09 12:31 AM
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