What happens when DRAM has more bandwidth than Layer 3 cache?

By: --- (---.delete@this.redheron.com), December 8, 2022 3:54 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on December 8, 2022 2:42 pm wrote:
> --- (---.delete@this.redheron.com) on December 8, 2022 10:32 am wrote:
> > Etienne (etienne_lorrain.delete@this.yahoo.fr) on December 8, 2022 6:20 am wrote:
> >
> > Look at what Apple does.
> > (a) Apple does not have L3. Instead we get something like the capacity of L3 with
> > the latency of L2 in the very large L2 caches. This is feasible if you cluster
> > cores to share an L2, something that makes sense for other reasons as well.
> > Various ARM designs have done this and this is what Intel E-cores do, isn't it?
> >
>
> It isn't.
> In Alder Lake and Raptor Lake E-core modules are sharing L3 cache with P-cores.
>
> ARM:
> AWS Graviton2 has decent L3 cache, but Graviton3's is twice bigger.
> Ampere Altra Max has rather small SLC. Probably too small to be considered L3 cache.
> As to high end Qualcomm/Microsoft, I would like to know myself. So far I was not able to find any info.

That was not my point.
My point was that a cluster of cores (certainly for Apple and some ARM, and I think for Intel E-cores) can share an L2, and if you're operating in a world like that, you may want to make the L2 large enough that (apparently) you no longer need an L3 in terms of capacity.
(That is essentially Apple's *apparent* design as far as CPU's goes.)

The rest of the post was then an explanation as to why, EVEN for such a design, something "L3-like" is required.
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 06:20 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Simon Farnsworth2022/12/08 07:22 AM
    bandwidth*delay productMichael S2022/12/08 08:06 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 10:44 AM
      What happens when DRAM has more bandwidth than Layer 3 cache?blaine2022/12/08 05:07 PM
  What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 07:32 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 08:05 AM
      What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 08:13 AM
        What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 01:56 PM
  What happens when DRAM has more bandwidth than Layer 3 cache?Peter E. fry2022/12/08 08:20 AM
  Programs do not see bandwidth. Programs only see latency. Heikki Kultala2022/12/08 08:26 AM
    Programs do not see bandwidth. Programs only see latency. Chester2022/12/08 11:07 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Doug S2022/12/08 09:31 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 10:32 AM
    What happens when DRAM has more bandwidth than Layer 3 cache?Michael S2022/12/08 02:42 PM
      What happens when DRAM has more bandwidth than Layer 3 cache?---2022/12/08 03:54 PM
        What happens when DRAM has more bandwidth than Layer 3 cache?Anon2022/12/20 06:46 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Andrey2022/12/08 03:10 PM
    What happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/14 03:20 AM
  What happens when DRAM has more bandwidth than Layer 3 cache?Gionatan Danti2022/12/09 12:31 AM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell tangerine? ūüćä