--- (---.delete@this.redheron.com) on January 27, 2023 9:31 am wrote:
>
> Outsiders obviously have to work with limited data; we can't prove anything,
> we can just point to patterns and say what they suggest to us.
>
> Having said that, I compared Pat with Steve Job's return to Apple, or even
> Satya's first two years. Both made it clear in their first year that it was
> no longer business as usual, that things had to be shaken up and changed.
> Conversely I don't see Pat as doing anything similar. Steve, for example, dealt with
> complexity (of a different sort, sure) by dramatically pruning the product line. But
> Pat has done nothing similar. Intel differentiators (whether AVX512 or accelerators)
> are used as a market segmentation mechanism, not as a way to grow the ecosystem.
> IMHO the fundamental problem with Intel is that engineers are not in charge. Finance controls one set of decisions,
> marketing controls another. Steve or Satya would have dealt with this by dramatic changes in those core areas;
> but Pat retains the dividend, in spite of everything, and retaining the marketing control (engineer effort spread
> over finely differentiated product segmentation, far too much making promises and setting schedules before it's
> known what is possible). Compare how Intel and AMD comport themselves in this respect.
>
> It's easy to mock Intel or complain for tribal reasons. The problem is,
> it's just as easy to do so for good, grounded, data-based reasons.



What I have found astounding and incomprehensible is the following fragment from the NYT article:

"She also concluded that the team should have spent more time on perfecting and testing its design using computer simulations. Finding bugs before they are in sample chips is less expensive, and would have made it possible to remove features to simplify the product, Ms. Rivera said. She has since moved to bolster Intel’s simulation and validation abilities."


I have done myself simulations of very large SoCs, including CPUs, so I am perfectly aware that a single simulation of the first minute of the booting sequence may need many days or even weeks, with the computing resources of a typical company.

Nevertheless, of all companies, I would expect for Intel to have the least difficulties in assembling enough computing resources to enable a rigorous validation of something like Sapphire Rapids before the tapeout.

Why they have not followed the standard methodology in this field, is a mystery.



In the past, I have found equally astounding and incomprehensible that Intel has always behaved as if they had never done any proper simulations of their future CMOS manufacturing processes and of the electrical characteristics of the semiconductor devices that would be fabricated with them.

They have always acted as if the poor performances, i.e. low clock frequencies and high power consumptions, had been last-minute surprises, which have forced them to execute various B plans.


After launching their first "10 nm" products in 2018, already after a few years of process development, Intel has needed more than 5 additional years of process optimization, to finally obtain the electrical device characteristics that would have been desirable since the beginning, which will be demonstrated in Raptor Lake Refresh (expected at the end of 2023).

Now, at the transition to their next process generation, Intel seems to exhibit the same kind of problem, of not being able to reach high clock frequencies in the new process, so they have been forced to retain only the mobile variant of Meteor Lake and scrap whatever was planned for desktop and replace it with Raptor Lake Refresh, exactly like they have done in the past with the Cannon Lake/Coffee Lake Refresh, Ice Lake/Comet Lake and Tiger Lake/Rocket Lake pairs.

Hopefully this time they will no longer need so many years until the new process will become better than the old process.