Article: Coverage of IEDM 2003: Day 1
By: David Wang (dwang.delete@this.realworldtech.com), December 10, 2003 4:31 pm
Room: Moderated Discussions
mas (mas769@hotmail.com) on 12/10/03 wrote:
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>"
>AMD discloses that its yield problem on the 130nm SOI process was due to the integration
>of Low-K materials into the process rather than SOI.
>"
>
>Now that is the killer line that will get you hits and looky sees all around the Web, lol.
AMD also talked about a few things like how they gradually modified the gate structure for SOI until it finally achieved the performance they were expecting. Apparently the transplanted gate structure performed rather sub-optimally.
AMD had some nice slides, and I've asked to see if I can get them to include with the article. However, the presenter won't be back in Germany until after the 19th. I'll either have to wait and see if he'll send the slides or just write it up without the slides.
According to the presenter, AMD was seeing quite a bit of defects from the edges of wafers, since the adhesion of the metal stack was sub-optimal. They were in fact flaking off, and causing more problems toward the center of the wafer.
---------------------------
>"
>AMD discloses that its yield problem on the 130nm SOI process was due to the integration
>of Low-K materials into the process rather than SOI.
>"
>
>Now that is the killer line that will get you hits and looky sees all around the Web, lol.
AMD also talked about a few things like how they gradually modified the gate structure for SOI until it finally achieved the performance they were expecting. Apparently the transplanted gate structure performed rather sub-optimally.
AMD had some nice slides, and I've asked to see if I can get them to include with the article. However, the presenter won't be back in Germany until after the 19th. I'll either have to wait and see if he'll send the slides or just write it up without the slides.
According to the presenter, AMD was seeing quite a bit of defects from the edges of wafers, since the adhesion of the metal stack was sub-optimal. They were in fact flaking off, and causing more problems toward the center of the wafer.
