mas (mas769@hotmail.com) on 12/11/03 wrote:
---------------------------
>David Wang (dwang@realworldtech.com) on 12/10/03 wrote:
>---------------------------
>>mas (mas769@hotmail.com) on 12/10/03 wrote:
>>---------------------------
>>>"
>>>AMD discloses that its yield problem on the 130nm SOI process was due to the integration
>>>of Low-K materials into the process rather than SOI.
>>>"
>>>
>>>Now that is the killer line that will get you hits and looky sees all around the Web, lol.
>>
>
>http://www.siliconinvestor.com/stocktalk/msg.gsp?msgid=19584598
>
>told you. :-). In fact I think yours was a Web exclusive.
>
>>AMD also talked about a few things like how they gradually modified the gate structure
>>for SOI until it finally achieved the performance they were expecting. Apparently
>>the transplanted gate structure performed rather sub-optimally.
>>
>>AMD had some nice slides, and I've asked to see if I can get them to include with
>>the article. However, the presenter won't be back in Germany until after the 19th.
>>I'll either have to wait and see if he'll send the slides or just write it up without the slides.
>>
>>According to the presenter, AMD was seeing quite a bit of defects from the edges
>>of wafers, since the adhesion of the metal stack was sub-optimal. They were in fact
>>flaking off, and causing more problems toward the center of the wafer.
>>

Forgot to ask how they cured their yield problems in the end and also sounds like the problems IBM have been having too with Low-K.

Also did they mention when they were having the problem and when it was fixed ?

>
>Fascinating. It just shows that these guys are almost like explorers going into
>unchartered territory where you never know what is lurking round the corner. You
>and Paul have produced a fine body of work here, don't get disheartened, we all
>read it and appreciate it even if we are not always vocal about it. :-)
>
>