New Silicon Insider article

Article: Wolves in CISC Clothing
By: Anonymous (not.delete@this.transmeta.com), January 17, 2004 3:52 pm
Room: Moderated Discussions
PiedPiper (piedpiper44@iprimus.com.au) on 1/12/04 wrote:
---------------------------
>Just read it another great article.
>
> quick question - how much would transmeta's design
> benifit from a nice fast offdie L3 cache, for the 16Mb
> of current x86 software images??
> OK i realise this might make it a poor choice as a
> platform for a lowe power pc, but that would help
> performance LOTS right?
>

Not really. The only way this would be much faster would be if the L3 cache was SRAM, and that's clearly out of the question cost and power wise. The TM5xxx has its DRAM controller on die anyway, so a DRAM based L3 of that size would not be much faster than a main memory access.

However, it would possibly be useful if Crusoe had an on-die embedded DRAM of ~2 MB, just to store the CMS code and critical data, but not all the translated x86 code (still in main memory).

Either way, when running within translated x86 code, the vast majority of the memory traffic is for x86-visible data (loads/stores) anyway, not i-cache accesses. The TM5xxx has a big 128 KB L1 i-cache, plus an 8 KB local program memory (LPM), both of which minimize thrashing between CMS itself and translated x86 code.

More details on all of this will be in Crusoe Exposed, Part 2. It will be published as an official RWT article as soon as it's revised and formatted.
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