By: Anonymous (nospam.delete@this.nospam.com), July 24, 2004 9:53 pm
Room: Moderated Discussions
>
>Just one thing, new Prescott chips have variable
>microcode size (stored in previously reserved fields of
>the header). I have seen updates 4000 bytes long
>...
>
Prescott is a very unusual chip in its use of microcode. There is a substantial amount of suspicion that this "microcode" is very rapidly approaching the level of a fully programmable hidden instruction set.
According to Intel's patents and the die plot analysis by Chip Architect (see below), the microcode is actually stored in the L2 unified cache and brought directly into the L1 trace cache as needed. This sure doesn't sound like the classical definition of microcode. In fact, it appears to be more like Transmeta's native ISA, just without the VLIW or code morphing parts.
It has even been suggested (see below) that Intel or others may sell custom microcode, for instance to add security features or enable hidden functionality. There is even a second micro-controller within the Prescott die (code named LaGrande), allegedly to handle control logic for this "native" instruction set. This is just a small fraction of the "dark silicon" that appears in the Prescott die yet no one outside of Intel has any clue what features it holds.
Supposedly the loadable microcode can be encrypted with full public key techniques, which would certainly be possible given the level of sophistication I've described above. Some of that dark silicon may very well be an RSA accelerator or the like (but not just for microcode decryption, obviously.)
So, in summary, there is apparently a *lot* more running inside Prescott than just the IA-32 (or now x86-64) instruction sets.
As far as reading the decrypted code directly out of the L2, that's a good idea. However, if secure encryption was one of their intended applications, this may be restricted even if you have the right probe equipment.
Let me know if you have any more information on this (or for that matter even a source where I can get the Prescott update blocks. I haven't owned an Intel CPU in years...) This sounds really interesting.
References:
- U.S. Patent 6549821 (loadable microcode)
- http://www.chip-architect.com/news/2003_04_20_Looking_at_Intels_Prescott_part2.html
>Just one thing, new Prescott chips have variable
>microcode size (stored in previously reserved fields of
>the header). I have seen updates 4000 bytes long
>...
>
Prescott is a very unusual chip in its use of microcode. There is a substantial amount of suspicion that this "microcode" is very rapidly approaching the level of a fully programmable hidden instruction set.
According to Intel's patents and the die plot analysis by Chip Architect (see below), the microcode is actually stored in the L2 unified cache and brought directly into the L1 trace cache as needed. This sure doesn't sound like the classical definition of microcode. In fact, it appears to be more like Transmeta's native ISA, just without the VLIW or code morphing parts.
It has even been suggested (see below) that Intel or others may sell custom microcode, for instance to add security features or enable hidden functionality. There is even a second micro-controller within the Prescott die (code named LaGrande), allegedly to handle control logic for this "native" instruction set. This is just a small fraction of the "dark silicon" that appears in the Prescott die yet no one outside of Intel has any clue what features it holds.
Supposedly the loadable microcode can be encrypted with full public key techniques, which would certainly be possible given the level of sophistication I've described above. Some of that dark silicon may very well be an RSA accelerator or the like (but not just for microcode decryption, obviously.)
So, in summary, there is apparently a *lot* more running inside Prescott than just the IA-32 (or now x86-64) instruction sets.
As far as reading the decrypted code directly out of the L2, that's a good idea. However, if secure encryption was one of their intended applications, this may be restricted even if you have the right probe equipment.
Let me know if you have any more information on this (or for that matter even a source where I can get the Prescott update blocks. I haven't owned an Intel CPU in years...) This sounds really interesting.
References:
- U.S. Patent 6549821 (loadable microcode)
- http://www.chip-architect.com/news/2003_04_20_Looking_at_Intels_Prescott_part2.html
