New Silicon Insider Article

Article: Sizing up the Super Heavyweights
By: Anonymous4 (i.delete@this.am.anonymous), October 16, 2004 9:39 pm
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 10/11/04 wrote:
---------------------------
>Paul DeMone has just finished his latest edition of Silicon Insider.

Paul, great read, two questions:

1) Why do you show 3 separate blocks of L2 cache per die on
figure 5. ? Is that an accurate physical or logical
representation of the power4/5 die? I was under the
impression that the L2 was shared between the cores. I
apologize in advance if I've missed something
elementary, I'm not an MPU architect (IANAMA).

2) Your estimate of 2.7 Ghz for Power5+ is interesting. Do
you think that will be the initial maximum or an eventual
maximum? I'm thinking you mean the final maximum.

If Power5+ never makes it to 2.7 Ghz, how will that
affect the eventual performance race between it and
Montecito ? I would assume it could have a great impact
judging by the numbers in table4, where the estimates
show Power5+ achieving near linear scaling in the SPEC
workloads and Linpack with very respectable scaling in
TPC/C. Plus, the estimates between it and Montecito look
very close.
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TopicPosted ByDate
New Silicon Insider ArticleDavid Kanter2004/10/11 04:43 AM
  Good read. Thanks again Paul. (NT)Michael Menietti2004/10/11 05:36 AM
  New Silicon Insider ArticleSingh, S.R.2004/10/11 05:44 AM
    New Silicon Insider ArticlePaul DeMone2004/10/11 05:55 AM
  New Silicon Insider Articletecate2004/10/11 08:52 AM
  core size: x86 vs IPFanonymous2004/10/11 10:43 AM
    Good Question. (NT)Chuck2004/10/12 07:22 AM
    core size: x86 vs IPFMichael S2004/10/12 09:53 AM
    K8 core size 52mm^2IlleglWpns2004/10/12 11:15 AM
    core size: x86 vs IPFPaul DeMone2004/10/12 12:10 PM
  New Silicon Insider ArticleJS2004/10/13 01:42 AM
  New Silicon Insider Articlemas2004/10/16 08:07 AM
  New Silicon Insider ArticleAnonymous42004/10/16 09:39 PM
    New Silicon Insider ArticlePaul DeMone2004/10/17 05:58 AM
  New Silicon Insider ArticleArun Ramakrishnan2004/10/22 07:48 AM
    New Silicon Insider ArticlePaul DeMone2004/10/22 09:38 AM
      New Silicon Insider ArticleDavid Kanter2004/10/22 10:04 PM
        New Silicon Insider ArticlePaul DeMone2004/10/23 05:02 AM
        New Silicon Insider ArticleArun Ramakrishnan2004/10/23 12:47 PM
      New Silicon Insider ArticleMichael S2004/10/23 10:38 AM
        New Silicon Insider ArticlePaul DeMone2004/10/23 12:10 PM
          New Silicon Insider ArticleMichael S2004/10/23 12:40 PM
  Do I see a flaw here?IntelUser20002004/10/27 04:43 PM
    Frequency is different for startersPaul DeMone2004/10/27 05:05 PM
      Frequency is different for startersIntelUser2004/10/27 05:28 PM
        Frequency is different for startersPaul DeMone2004/10/27 06:49 PM
          Frequency is different for startersIntelUser20002004/10/27 07:45 PM
  New Silicon Insider ArticleIntelUser20002004/11/01 09:13 AM
    New Silicon Insider Articleanonymous2004/11/02 08:46 AM
      New Silicon Insider ArticleChuck2004/11/02 09:33 AM
        New Silicon Insider ArticleSingh, S.R.2004/11/02 11:21 AM
          New Silicon Insider ArticleJosé Javier Zarate2004/11/02 02:14 PM
            New Silicon Insider ArticleSingh, S.R.2004/11/02 06:47 PM
        New Silicon Insider Articleanonymous2004/11/03 02:04 PM
          New Silicon Insider Articleanonymous2004/11/03 02:07 PM
  New Silicon Insider ArticleIntelUser20002004/11/04 10:30 AM
    New Silicon Insider ArticleIntelUser20002004/11/04 08:38 PM
      New Silicon Insider ArticleDavid Kanter2004/11/05 07:44 AM
        New Silicon Insider ArticleIntelUser20002004/11/08 07:23 PM
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